Product Description |
Optimized for 5 V mixed-signal applications, the C5 process family from ON Semiconductor offers a medium-density, high-performance mixed-signal technology capable of integrating complex analog functions, digital content and 20 V capability. This process delivers the advantages of a dedicated mixed-signal 0.5 µm process without the costs associated with the extra mask steps of a BCD process. Low-voltage transistors are also available for the 0.5 µm process making it well-suited for low-power applications.
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Features |
- 2 or 3 metal layers
- Poly to poly capacitors
- EEPROM
- Schottky diodes
- High voltage I/O – 12/20 V
- High-resistance poly
- Low-voltage modules
Process Characteristics
Operating Voltage |
5, 12 V |
Substrate Material |
P-Type, Bulk or EPI |
Drawn Transistor Length |
0.6 µm |
Gate Oxide Thickness |
13.5 nm |
Contact/Via Size |
0.5 µm |
Contacted Gate Pitch |
3.9 µm |
Top Metal Thickness |
675 nm |
Contacted Metal Pitch |
Metal 1 |
1.5 µm |
Metal 2, 3 |
1.6 µm |
Metal Composition |
TiN/AlCu/TiN |
Sample Process Options
|
Mask Layers* |
Standard CMOS with 20 V extended drain |
13/15 |
Plus double poly cap |
14/16 |
All of the above plus 1,000 Ω/square resistor |
15/17 |
All of the above plus 12 V gate |
16/18 |
All of the above plus low Vt devices |
19/21 |
* 2 Metal/3 Metal.
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Device Characteristics |
(All Values Typical at 25°C)
High-Voltage Transistors
12 V Dual Gate Nested Drain
N-Ch 12 V (NU) |
Typical Value |
Unit |
Vt |
0.95 |
V |
Idsat |
450 |
µA/µm |
BVDSS |
19 |
V |
P-Ch 12 V (PU) |
Vt |
-1.6 |
V |
Idsat |
-110 |
µA/µm |
BVDSS |
-14.5 |
V |
20 V Extended Drain, 15 V Gate
N-Ch 20 V (NX) |
Typical Value |
Unit |
Vt |
0.95 |
V |
Idsat |
400 |
µA/µm |
BVDSS |
28 |
V |
P-Ch 20 V (PU) |
Vt |
-1.65 |
V |
Idsat |
-130 |
µA/µm |
BVDSS |
-28 |
V |
20 V Extended Drain, 5 V Gate
N-Ch 20 V (NT) |
Typical Value |
Unit |
Vt |
0.75 |
V |
Idsat |
145 |
µA/µm |
BVDSS |
28 |
V |
P-Ch 20 V (PT) |
Vt |
-1.0 |
V |
Idsat |
-55 |
µA/µm |
BVDSS |
-28 |
V |
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Standard Transistors
N-Channel |
Typical Value |
Unit |
Vt |
0.7 |
V |
Idsat |
450 |
µA/µm |
P-Channel |
Vt |
-0.9 |
V |
Idsat |
-260 |
µA/µm |
Resistors
|
Typical Value |
Unit |
Poly |
25 |
Ω/square |
Hi-R Poly |
1000 |
Ω/square |
N-Diffusion |
80 |
Ω/square |
P-Diffusion |
110 |
Ω/square |
N-Well |
855 |
Ω/square |
Capacitors
Poly-Poly |
Typical Value |
Unit |
Area |
0.9 |
fF/µm² |
Periphery |
0.065 |
fF/µm |
|
|
Libraries |
(All values typical at 3.3 V, 25°C)
Front-End Digital Design |
Digital |
Synthesis Libraries |
Simulation Libraries |
Analog - General Design Information (GDI) |
Design Rules |
Spice Models |
Digital Design |
High Performance Core |
4.2 K gates/mm² * |
1.58 µW/MHz/gate |
103 ps gate delay (2 Input NAND, fanout = 2) |
Tall Pads for high I/O count designs |
86 µm in-line pad pitch |
60 µm staggered pad pitch |
558 µm pad height |
Mixed-Signal Design |
Cadence Technology File |
Cadence Transistor Library |
Mixed-Signal Core |
Separate substrate bus for reduced digital noise |
7.4 K gates/mm² * |
0.63 µW/MHz/gate |
558 µm pad height |
128 ps gate delay (2 Input NAND, fanout = 2) |
Mixed Signal Short Pads for high logic contact designs |
135 µm in-line pad pitch |
388 µm pad height |
Mixed-Signal Medium Height Pads |
86 µm in-line pad pitch |
567 µm pad height |
* Routed gate density.
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Memory Options |
SRAM |
Single Port Synchronous* |
191 µm²/bit (64 k bit memory) |
Dual Port Synchronous* |
567 µm²/bit (64 k bit memory) |
ROM |
Asynchronous* |
14.65 µm²/bit (64 k bit memory) |
* Compiled
EEPROM |
NASTEE (No Additional Steps EEPROM) |
Vector (1x4 up to 1x32) |
Array (2x4 up to 32x32) |
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CAD Tool Compatibility |
Digital Design |
Synopsys Design Compiler |
Cadence Verilog |
Analog Design |
Cadence DFII (4.4.6) |
Spectre |
Place and Route |
Synopsys Apollo, Astro |
Cadence Silicon Ensemble |
Physical Verification |
Mentor Calibre |
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For more information please contact your local sales support at www.onsemi.com |