时钟驱动器,1:5 差分,双路 LVDS,2.5 V

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MC100EP210S 是一款低歪曲率 1:5 双路差分驱动器,在设计时考虑到了 LVDS 时钟分配。LVDS 或 LVPECL 输入信号为差分信号,并且信号被分配为五个相同的差分 LVDS 输出。EP210S 可特别保证低输出-输出歪曲率。优化的设计、布局和处理最大程度降低了器件内和器件到器件的歪曲率。整个输入提供两个内部 50 欧姆电阻。对于 LVDS 输入,应断开 VTA 和 VTB 引脚的连接。对于 LVPECL 输入,应将 VTA 和 VTB 引脚连接至 VTT(VCC-2.0 V)电源。设计人员可充分利用 EP210S 的性能,在底板或主板上分配低歪曲率 LVDS 时钟。在无信号条件下,应对差分输入进行特别考虑以防止不稳定。

  • High Performance Logic for test systems and work stations. Clock fan out in routers, switches and other networking applications
  • 20 ps Typical Output-to-Output Skew
  • 85 ps Typical Device-to-Device Skew
  • 550 ps Typical Propagation Delay
  • The 100 Series contains temperature compensation.
  • Maximum Frequency > 1 Ghz
  • Operating Range: VCC = 2.375 V to 2.625 V with VEE = 0 V
  • Internal 50Ω Input Termination Resistors
  • LVDS Input/Output Compatible
  • Pb-Free Packages are Available

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MC100EP210SFAG

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Active

CAD Model

Pb

A

H

P

LQFP-32

2

260

JTRAY

250

Y

Buffer

2

1:5

LVDS

LVDS

2.5

0.2

25

0.55

200

1000

-

Price N/A

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MC100EP210SFAR2G

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Active

CAD Model

Pb

A

H

P

LQFP-32

2

260

REEL

2000

Y

Buffer

2

1:5

LVDS

LVDS

2.5

0.2

25

0.55

200

1000

-

Price N/A

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MC100EP210SMNG

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Active

CAD Model

Pb

A

H

P

QFN-32

1

260

TUBE

74

Y

Buffer

2

1:5

LVDS

LVDS

2.5

0.2

25

0.55

200

1000

-

Price N/A

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MC100EP210SMNR4G

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Active

CAD Model

Pb

A

H

P

QFN-32

1

260

REEL

1000

Y

Buffer

2

1:5

LVDS

LVDS

2.5

0.2

25

0.55

200

1000

-

Price N/A

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