Arithmetic Functions | MC100LVEL34

3.3 V ECL ÷·2，÷·4，÷·8 分频器

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MC100LVEL34 是一款低歪曲率 2、4、8 分频时钟生成芯片，明确适用于低歪曲率时钟生成应用。内部分频器互相同步，因此公共输出边全部精确对齐。仅为此器件提供 VBB 引脚，即内部产生的供应电压。对于单端输入情况，未使用的差分输入将作为开关参考电压联接 VBB。VBB 还可将 AC 耦合输入重偏置。使用时，通过 0.01 F 电容器对 VBB 和 VCC 进行去耦合，并将源或汲电流限制为 0.5 mA。不使用时，VBB 应保持开路。公共启用 (ENbar) 是同步的，因此内部分频器仅在内部时钟已在低电平状态时启用/禁用。这样会避免当设备启用/禁用时在内部时钟上产生短时钟脉冲，这种情况可能发生在异步控制中。内部矮脉冲可能导致内部分频器级之间的同步丢失。内部启用触发器在输入时钟的下降边进行计时，因此，所有相关规格限制都参考到时钟输入的负边。启动时，内部触发器将达到随机状态；主时钟重置 (MR) 输入实现内部分频器之间以及系统中多个 LVEL34 的同步。

  • 50 ps Typical Output-to-Output Skew
  • Synchronous Enable/Disable
  • Master Reset for Synchronization
  • 1.5 GHz Toggle Frequency
  • The 100 Series Contains Temperature Compensation.
  • PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V
  • Open Input Default State
  • LVDS Input Compatible
  • Pb-Free Packages are Available

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MC100LVEL34DR2G

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CAD Model

Pb

A

H

P

SOIC-16

751B-05

1

260

REEL

2500

Y

Divider

LVDS

ECL

3.3

1500

0.7

400

Price N/A

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MC100LVEL34DTR2G

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CAD Model

Pb

A

H

P

TSSOP-16

948F-01

1

260

REEL

2500

Y

Divider

LVDS

ECL

3.3

1500

0.7

400

Price N/A

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