Flip-Flops, Latches & Registers | MC10EP51

3.3 V / 5.0 V ECL D Flip-Flop with Reset and Differential Clock

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The MC10/100EP51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices.

The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop.

The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLKbar input will be biased at VCC / 2.

  • ATE
  • 350ps Typical Propagation Delay
  • Maximum Frequency > 3 Ghz Typical
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Pb-Free Packages are Available

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ON Target

Type

Bits

Input Level

Output Level

VCC Typ (V)

tJitter Typ (ps)

tpd Typ (ns)

tsu Min (ns)

th Min (ns)

trec Typ (ns)

tR & tF Max (ps)

fToggle Typ (MHz)

Reference Price

MC10EP51DR2G

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Active

CAD Model

Pb

A

H

P

SOIC-8

751-07

1

260

REEL

2500

Y

D-Type

1

ECL

ECL

5

0.2

0.375

0.1

0.1

0.15

170

3000

Price N/A

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MC10EP51DTG

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Active

CAD Model

Pb

A

H

P

TSSOP-8

948R-02

3

260

TUBE

100

Y

D-Type

1

ECL

ECL

5

0.2

0.375

0.1

0.1

0.15

170

3000

Price N/A

More Details

MC10EP51MNTAG

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Active

CAD Model

Pb

A

H

P

DFN-8

506AA

1

260

REEL

1000

Y

D-Type

1

ECL

ECL

5

0.2

0.375

0.1

0.1

0.15

170

3000

Price N/A

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