D Flip-Flops and JK Flip-Flops | MC14027B

Dual JK Flip Flop

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The MC14027B dual JK flip flop has independent J, K, Clock (C), Set (S) and Reset (R) inputs for each flip-flop. These devices may be used in control, register, or toggle functions.

  • Diode Protection on All Inputs
  • Supply Voltage Range = 3.0 Vdc to 18 Vdc
  • Logic Swing Independent of Fanout
  • Logic Edge-Clocked Flip-Flop Design: Logic state is retained indefinitely with clock level either high or low;information is transferred to the output only on the positive-going edgeof the clock pulse
  • Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range
  • Pin-for-Pin Replacement for CD4027B
  • Pb-Free Packages are Available*

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MC14027BDG

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CAD Model

Pb

A

H

P

SOIC-16

751B-05

1

260

TUBE

48

N

JK-Type

2

3

18

150

2.25

Price N/A

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MC14027BDR2G

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Pb

A

H

P

SOIC-16

751B-05

1

260

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2500

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JK-Type

2

3

18

150

2.25

$0.2251

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NLV14027BDG

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CAD Model

Pb

A

H

P

SOIC-16

751B-05

1

260

TUBE

48

N

JK-Type

2

3

18

150

2.25

Price N/A

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NLV14027BDR2G

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CAD Model

Pb

A

H

P

SOIC-16

751B-05

1

260

REEL

2500

N

JK-Type

2

3

18

150

2.25

$0.2137

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可靠性数据

Die Related Summary Data

Device: MC14027BDG

Equivalent to wafer fab process: CMOS STD

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等效器件小时

平均故障间隔时间/平均无故障时间（按小时计算）

FITS

CMOS STD

3

3597164517

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Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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