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Drivers & Fanout Buffers | NB3RL02
概览
The NB3RL02 is a low-skew, low jitter 1:2 clock fan-out buffer, ideal for use in portable end-equipment, such as mobile phones. With integrated LDO and output control circuitry. The MCLK_IN pin has an AC coupling capacitor and will directly accept a square or sine wave clock input, such as a temperature compensated crystal oscillator (TCXO). The minimum acceptable input amplitude of the sine wave is 300 mV peak-to-peak. The two clock outputs are enabled by control inputs CLK_REQ1 and CLK_REQ2. The NB3RL02 has an integrated Low-Drop-Out (LDO) voltage regulator which accepts input voltages from 2.3 V to 5.5 V and outputs 1.8 V at Iout = 50 mA. This 1.8 V supply is externally available to provide regulated power to peripheral devices, such as a TCXO. The adaptive clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution lines. The NB3RL02 is offered in a 0.4 mm pitch wafer-level-chip-scale (WLCS) package (0.77 mm x 1.57 mm) and is optimized for very low standby current consumption.
应用
- Wireless LAN
- FM Radio
- WiMAX
- Wireless BT
终端产品
- Cellular Phones
- Global Positioning Systems (GPS)
特性
- Low Additive Noise: -149 dBc/Hz at 10 kHz Offset Phase Noise
- Regulated 1.8 V Output Supply Available for External Clock Source,
ie. TCX0 - Ultra-Small Package: 8-ball: 0.4 mm Pitch WLCS (0.77 mm x 1.57 mm)
- ESD Performance Exceeds JESD 22: 2000 V Human Body Model
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NB3RL02FCT2G
Active
Pb
A
H
P
WLCSP-8
1
260
DSFTP
3000
N
Buffer
2
1:2
Square Wave
Square Wave
5
0.37
500
12
5000
26
~NA~
Price N/A
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