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NB4L16M: Translator, 2.5 V / 3.3 V, 5 Gb/s Multi Level, Clock/Data Input to CML, Driver / Receiver / Buffer, with Internal Termination

Overview
Specifications
Datasheet: Translator, 2.5 V / 3.3 V, 5 Gb/s Multi Level, Clock/Data Input to CML, Driver / Receiver / Buffer, with Internal Termination
Rev. 3 (766.0kB)
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Product Overview
产品说明
The NB4L16M is a differential driver/receiver/buffer/translator which can accept LVPECL, LVDS, CML, LVCMOS/LVTTL and produce 400 mV CML output. The device is housed in a 3x3 mm 16 pin QFN package.
Differential inputs incorporate internal 50 Ω termination resistors and accept LVPECL (Positive ECL), LVTTL/LVCMOS, CML, or LVDS. The differential 16 mA CML output provides matching internal 50 Ω termination, and 400 mV output swing when externally receiver terminated, 50 Ω to VCC. These features provide transmission line termination on chip, at the receiver and driver end, eliminating any use of additional external components.
The VBB, an internally generated voltage supply, is available to this device only. For single ended input configuration, the unused complementary differential input is connected to VBB as a switching reference voltage. The VBB reference output can be used also to re-bias capacitor coupled differential or single ended output signals. For the capacitor coupled input signals, VBB should be connected to the VTD pin and bypassed to ground with a 0.01 µF capacitor. When not used VBB should be left open.
特性
 
  • Maximum Input Clock Frequency > 3.5 GHz Typical
  • Maximum Input Data Frequency > 5 Gb/s Typical
  • 220 ps Typical Propagation Delay
  • 65 ps Typical Rise and Fall Times
  • CML Output with Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V
  • CML Output Level (400 mV Peak-to-Peak Output), Differential Output Only
  • 50 Ω Internal Input and Output Termination Resistors
  • Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices
  • Pb-Free Packages are Available
应用
  • OC-3 to OC-48 SONET/SDH Data Buffering
  • 3.2Gb/s XAUI Data Buffering
技术文档及设计资源
应用注释 (9) 封装图纸 (1)
仿真模型 (1) 评估板文档 (1)
数据表 (1)  
评估/开发工具信息
产品 状况 Compliance 简短说明 行动
NB4L16MMNEVB Active
Translator with Internal Termination Evaluation Board
Avnet (2015-07-09) : 2
Digikey (2015-07-09) : 2
供货情况和样品
产品
状况
Compliance
具体说明
封装
MSL*
容器
预算价格 (1千个数量的单价)
类型
外形
类型
数量
NB4L16MMNG Active
Pb-free
Halide free
Translator, 2.5 V / 3.3 V, 5 Gb/s Multi Level, Clock/Data Input to CML, Driver / Receiver / Buffer, with Internal Termination QFN-16 485AE 1 Tube 123 Contact Sales Office
NB4L16MMNR2G Active
Pb-free
Halide free
Translator, 2.5 V / 3.3 V, 5 Gb/s Multi Level, Clock/Data Input to CML, Driver / Receiver / Buffer, with Internal Termination QFN-16 485AE 1 Tape and Reel 3000 Contact Sales Office
表面贴装器件的潮湿敏感度等级(MSL)(260°C回流温度时测量无铅,235°C回流温度时测量含铅)
市场订货至交货的时间(周) : 2 to 4
Avnet   (2015-07-09) : <1K
Mouser   (2015-07-09) : <1K
ON Semiconductor   (2015-07-08) : 8,979
PandS   (2015-07-09) : <1K
市场订货至交货的时间(周) : 13 to 16
Datasheet: Translator, 2.5 V / 3.3 V, 5 Gb/s Multi Level, Clock/Data Input to CML, Driver / Receiver / Buffer, with Internal Termination
Rev. 3 (766.0kB)
»查看材料成分
»产品更改通知 (7)
Product Overview

Product Compliance Status Description Type Channels Input / Output Ratio Input Level Output Level VCC Typ (V) tJitterRMS Typ (ps) tskew(o-o) Max (ps) tpd Typ (ns) tR & tF Max (ps) fmaxClock Typ (MHz) fmaxData Typ (Mbps) Package Type
 Pb-free 
 Halide free 
 Active     Translator, 2.5 V / 3.3 V, 5 Gb/s Multi Level, Clock/Data Input to CML, Driver / Receiver / Buffer, with Internal Termination   Signal Driver   1   1:1 
 CML 
 CMOS 
 ECL 
 LVDS 
 TTL 
 CML 
 2.5 
 3.3 
 0.2   10   0.265   90   3500   5000   QFN-16 
 Pb-free 
 Halide free 
 Active     Translator, 2.5 V / 3.3 V, 5 Gb/s Multi Level, Clock/Data Input to CML, Driver / Receiver / Buffer, with Internal Termination   Signal Driver   1   1:1 
 CML 
 CMOS 
 ECL 
 LVDS 
 TTL 
 CML 
 2.5 
 3.3 
 0.2   10   0.265   90   3500   5000   QFN-16 
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