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NB4N11M: Multi Level Clock / Data Input to CML Receiver / Buffer / Translator, 2.5 Gbps, 3.3 V

Overview
Specifications
Datasheet: 3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator
Rev. 1 (223.0kB)
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Product Overview
产品说明
The NB4N11M is a differential 1−to−2 clock/data distribution/translation chip with CML output structure, targeted for high−speed clock/data applications. The device is functionally equivalent to the EP11, LVEP11, SG11 or 7L11M devices. The device produces two identical differential output copies of clock or data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such, NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications.

Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS. The CML outputs are 16 mA open collector which requires resistor (RL) load path to VTT termination voltage. The open collector CML outputs must be terminated to VTT at power up. Differential outputs produces current mode logic (CML) compatible levels when receiver loaded with 50 Ω or 25 Ω loads connected to 1.8 V, 2.5 V or 3.3 V supplies. This simplifies device interface by eliminating a need for coupling capacitors.
特性
 
  • Maximum Input Clock Frequency > 2.5 GHz
  • Maximum Input Data Rate > 2.5 Gb/s
  • Typically 1 ps of RMS Clock Jitter
  • Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, RL = 25 Ω
  • 420 ps Typical Propagation Delay
  • 150 ps Typical Rise and Fall Times
  • Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V and VTT = 1.8 V to 3.6 V
  • Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and GigaComm Devices
  • These are Pb-Free Devices
应用
  • Clock distribution in high speed networking and Automated Test Equipment.
技术文档及设计资源
应用注释 (4) 封装图纸 (1)
仿真模型 (2) 评估板文档 (2)
数据表 (1)  
评估/开发工具信息
产品 状况 Compliance 简短说明 行动
NB4N11MDTEVB Active
Clock/Data Input Evaluation Board
Avnet (2015-07-09) : 2
供货情况和样品
产品
状况
Compliance
具体说明
封装
MSL*
容器
预算价格 (1千个数量的单价)
类型
外形
类型
数量
NB4N11MDTG Active
Pb-free
Halide free
Multi Level Clock / Data Input to CML Receiver / Buffer / Translator, 2.5 Gbps, 3.3 V TSSOP-8 948R-02 3 Tube 100 Contact Sales Office
NB4N11MDTR2G Active
Pb-free
Halide free
Multi Level Clock / Data Input to CML Receiver / Buffer / Translator, 2.5 Gbps, 3.3 V TSSOP-8 948R-02 3 Tape and Reel 2500 Contact Sales Office
表面贴装器件的潮湿敏感度等级(MSL)(260°C回流温度时测量无铅,235°C回流温度时测量含铅)
市场订货至交货的时间(周) : 2 to 4
Avnet   (2015-07-09) : <100
Chip1Stop   (2015-07-09) : <100
Mouser   (2015-07-09) : <100
ON Semiconductor   (2015-07-08) : 13,600
PandS   (2015-07-09) : <100
市场订货至交货的时间(周) : 4 to 8
PandS   (2015-07-09) : >1K
Datasheet: 3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator
Rev. 1 (223.0kB)
»浏览可靠性数据
»查看材料成分
»产品更改通知 (4)
Product Overview

Product Compliance Status Description Type Channels Input / Output Ratio Input Level Output Level VCC Typ (V) tJitterRMS Typ (ps) tskew(o-o) Max (ps) tpd Typ (ns) tR & tF Max (ps) fmaxClock Typ (MHz) fmaxData Typ (Mbps) Package Type
 Pb-free 
 Halide free 
 Active     Multi Level Clock / Data Input to CML Receiver / Buffer / Translator, 2.5 Gbps, 3.3 V   Buffer   1   1:2 
 CML 
 LVCMOS 
 LVDS 
 LVPECL 
 LVTTL 
 CML   3.3   1   25   0.42   300   2500   2500   TSSOP-8 
 Pb-free 
 Halide free 
 Active     Multi Level Clock / Data Input to CML Receiver / Buffer / Translator, 2.5 Gbps, 3.3 V   Buffer   1   1:2 
 CML 
 LVCMOS 
 LVDS 
 LVPECL 
 LVTTL 
 CML   3.3   1   25   0.42   300   2500   2500   TSSOP-8 
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