Drivers & Fanout Buffers | NB3M8T3910G

差分时钟扇出缓冲器，带 LVCMOS 参考输出，可配置，2.5 V/3.3 V 3:1:10

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NB3M8T3910G 是一款 3:1:10 时钟扇出缓冲器，基于 2.5 V / 3.3 V 核心 VDD 和灵活的 3.3 V / 2.5 V VDDO 电源 (VDDO ≤ VDD) 运行。3:1 Mux 在晶体振荡器输入之间选择，或者选择两个能够接受 LVPECL、LVDS、HCSL 或 SSTL 电平的差分时钟输入之一。MUX 选择线路 SEL0 和 SEL1 接受 LVCMOS 或 LVTTL电平，根据表 3 选择输入。 选择时钟输入时，晶体输入禁用。差分输出由两组输出组成，每组五个差分输出，每组均可独立于模式配置为 LVPECL、LVDS、HCSL。每组差分输出对均根据表 6 使用 LVCMOS 或 LVTTL 电平配置一对 MODEAx/Bx 选择线路。 时钟输入电平和输出状态根据表 5 确定。 单端 LVCMOS 输出 REFOUT 根据表 4，使用 LVCMOS / LVTTL 电平由 OE_SE 控制线路进行同步启用。对于高于 250 MHz 的时钟频率，REFOUT 线路应禁用。

  • Clock Distrubtion
  • Telecom
  • Networking
  • Backplane
  • High End Computing
  • Wireless and Wired Infrastructure
  • Servers
  • Ethernet Switch/Routers
  • ATE, Test and Measurement
  • Crystal, Single-Ended or Differential Input Reference Clocks
  • Differential Input Pair can Accept: LVPECL, LVDS, HCSL, SSTL
  • Two Output Banks: Each has Five Differential Outputs Configurable as LVPECL, LVDS, or HCSL by SMODEAx/Bx Pins
  • One Single−Ended LVCMOS Output with Synchronous OE Control
  • LVCMOS/LVTTL Interface Levels for all Control Inputs
  • Clock Frequency: Up to 1400 Mhz, Typical
  • Output Skew: 50 ps (Max)
  • Additive RMS Jitter <0.03 ps (156.25 MHz, Typical)
  • Input to Output Propagation Delay (900 ps Typical)
  • Operating Supply Modes VDD/VDDO: 2.5 V/2.5 V, 3.3 V/3.3 V or 3.3 V/2.5 V
  • Industrial Temperature Range −40°C to 85°C

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NB3M8T3910GMNTWG

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Active

CAD Model

Pb

A

H

P

QFN-48

485AJ

1

260

REEL

2500

Y

Buffer

1

3:1:10

SSTL

LVPECL

3.3

0.03

50

0.9

325

1400

-

Price N/A

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