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/Title (NB3N51044 - 3.3 V, Crystal to 100 MHz / 125 MHz Quad HCSL / LVDS Clock Generator)
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ON Semiconductor
NB3N51044 - 3.3 V, Crystal to 100 MHz / 125 MHz Quad HCSL / LVDS Clock Generator
The NB3N51044 is a precision, low phase noise clock generator that
supports PCI Express and sRIO clock requirements. The device
accepts a 25 MHz fundamental mode parallel resonant crystal or a
25 MHz single ended reference clock signal and generates four
differential HCSL/LVDS outputs (See Figure 10 for LVDS interface)
of 100 MHz or 125 MHz clock frequency based on frequency select
input F_SEL. NB3N51044 is configurable to bypass the PLL from
signal path using BYPASS, and provides the output frequency through
the divider network. All clock outputs can be individually enabled /
disabled through hardware input pins OE[3:0]. In addition, device can
be reset using Master Reset input pin MR_OE#.
2017-09-25T14:35:20-07:00
BroadVision, Inc.
2020-10-16T10:27:25+08:00
2020-10-16T10:27:25+08:00
Acrobat Distiller 10.0.0 (Windows)
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