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Care in compensating a PFC stage can improve power factor and lower total harmonic distortion 

 由 Joel Turchi 发布 - 2015-06-22 12:54:26.0

Figure 1  - The output voltage exhibits a ripple at twice the line frequency

 

Figure 1 shows the line current (black trace) and the line voltage (blue trace) as a function of time. As a result of the PFC function, both of them are sinusoidal. Thus, the power provided to the load has the shape of a square sinusoid as shown by the red trace. Now, as suggested by the red dashed line, the output power is generally constant and the provided power matches the load demand in average. There are periods of time for which the PFC stage provides more power than needed (see “+” sign area) and the output capacitor absorbs this excess of energy. On the other hand, a second phase follows when the PFC stage supplies less power than necessary (see “-” sign area) and the output capacitor discharges to compensate the lack of energy.  The output voltage consequently (green trace) exhibits a ripple at twice the line frequency (typically 100 Hz in Europe, 120 Hz in US). This low-frequency ripple is inherent to the PFC function.

Now, traditional current shaping techniques require the control signal (provided by the regulation circuitry) to be a slowly-varying signal. If not, the line current will be distorted because the loop will react to the ripple. Hence, the regulation loop must reject this ripple, which is practically done by setting a very low bandwidth (in the range of 20 Hz).  That is why PFC systems are slow systems by essence.

Still the control signal is not ripple free.  Actually, as shown by Figure 2, it is generally provided by a type-2 compensator which amplifies the error between a portion of the output voltage and a reference. Hence, we can show that as sketched by Figure 3, vcontrol(t) exhibits a ripple at twice the line frequency, π to 3π/2 phase-shifted with respect to the output voltage ripple.

This ac component causes some current distortion.

Our PFC stage is designed to draw the following ideal current  where K is a constant and Vcontrol a ripple-free, slowly-varying signal. Unfortunately, the real absorbed current is:   where vcontrol(t) ac component causes some distortion.

 

Let’s compute the actual input current:

 (1)

 

Few manipulations could lead to the following equation: 

(2)

 

They show that the vcontrol(t)ripple provides a second fundamental component (blue term of equation (2)) that can be put in phase if the vcontrol(t)ripple is 3π/2 phase-shifted with respect to the output voltage ripple  . There is above all a third harmonic component (red term) which can only be minimized by limiting the relative part of the vcontrol(t)ripple in the control signal. The loop should hence be designed to strongly attenuate the ratio vcontrol(t)ripple over Vcontrol (vcontrol(t)dc value).

Figure 2 – Type-2 compensation

 

 

Figure 3 – Control signal ripple

 

From this, we can deduce:

- The vcontrol(t)phase should be optimized to avoid displacement of the line current fundamental. Practically, this leads vcontrol(t)to peak at the top of the input voltage (place the high-frequency pole as low a frequency as possible)

- It is desirable to operate with high vcontrol(t)dc values to minimize . To that extent, feedforward techniques that reduce the PWM gain as the line amplitude increases is of great help.

Now be careful. Feedforward consists of sensing the line magnitude and injecting this information within the current shaping circuitry. Again, any ac ripple in this signal will cause some distortion as shown by below equation:

(3)

Where:

  • vFF(t) is the feedforward signal (typically an averaged portion of the input voltage).
  •   is the signal phase 

Nothing is perfect!

Care must then been applied with feedforward as well and if it uses the mean input voltage, a 2-pole approach is probably to be preferred for building this average-based feedforward signal...

 

 

 

 

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