Product Description |
Providing the density of a 0.35 µm digital process, analog/mixed-signal capability and high voltage, the ON Semiconductor Intelligent Interface Technology I3T80 process is the answer to the need for increased digital content in a mixed-signal and/or high voltage environment. Featuring high voltage devices up to 80 V as well as digital and analog operation at 3.3 V, the I3T80 process family features a wide range of capabilities in a single IC.
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Features |
- 3 to 5 metal layers
- Metal to metal (MIM) linear capacitors
- High, medium, and low resistivity polysilicon resistors
- Floating high-voltage NDMOS and PDMOS transistors
- Floating medium-voltage NDMOS
- Floating high- and low-voltage diodes
- Medium-voltage NPN bipolar transistors
- Medium-voltage PNP bipolar transistors (collector grounded, high and low gain)
- Zener zap diode for OTP• Buried zener diode for clamping
- Polysilicon clamping diode
- High- and medium-voltage floating metal capacitors
- Deep n+ doped guard rings
Process Characteristics
Operating Voltage |
3.3 V |
Substrate Material |
N-epitaxy on P-sub, retrograde wells |
Drawn Transistor Length |
0.35 µm |
Gate Oxide Thickness |
7.0 nm |
Contact/Via Size |
0.4 µm |
Contacted Gate Pitch |
1.3 µm |
Top Metal Thickness |
1020 nm |
Metal Pitch |
Metal 1 |
1.0 µm |
Metal 2 |
1.1 µm |
Top Metal |
1.4 µm |
Contacted Metal Pitch |
Metal 1/CNT |
1.1 µm |
Metal 1/Via 1 |
1.2 µm |
Metal 2 to Top 1/Via |
1.2 µm |
Metal Composition |
AI/Cu |
Isolation |
LOCOS |
ILD Planarization |
USG/BPTEOS+CMP |
IMD Planarization |
HDP/PETEOS+CMP |
Sample Process Options
|
Mask Layers |
3 metal, 80 V, MIMC, HIPO, OTP |
23 |
4 metal, 80 V, MIMC, HIPO, OTP |
25 |
4 metal, 80 V, MIMC, HIPO, OTP, Flash EEPROM |
28 |
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Device Characteristics |
(All Values Typical at 25°C)
Low-Voltage Transistors
NMOS Transistor |
Typical
Value |
Unit |
Vt
(10/0.35, linear extrapolated) |
0.59 |
V |
Vmax=Vbd |
3.6 |
V |
IDS
(10/0.35,
Vds=Vgs=3.3 V) |
530 |
µA/µm |
PMOS Transistor |
Vt (10/0.35, linear extrapolated) |
-0.57 |
V |
Vmax=Vbd |
-3.6 |
V |
IDS
(10/0.35, Vds=Vgs=3.3 V) |
-250 |
µA/µm |
Diodes
Zener Diode: PBZD (a=2µm) |
Typical
Value |
Unit |
Vz @ 100 µA |
4.6 |
V |
Rzener |
45 |
Ω |
Ileak @ Vz=0.5 V |
200 |
nA |
Zapping Zener Diode for OTP: UZZD |
Vz @ 1 A |
1.5 |
V |
Vbd @ 10 mA |
4.5 |
V |
Ileak_max @ Vz= 1 V |
1.4 |
mA |
Floating High Voltage Diode: FID80 |
Vak_reverse, la=-100 nA |
>80 |
V |
Vak_forw, lk=100 µA |
0.79 |
V |
Isub/IA, Va=0.7 V |
0.5 |
% |
Poly Diode for Gate Clamping: POLYD |
Vreverse @ Ia=10 µA |
6.8 |
V |
Ileak/W @ Vrev=3.6 V |
<20 |
nA/µm |
Bipolar Transistors
Vertical Medium-Voltage PNP: VPB (Parameter, E_area=0.64µm²) |
Typical
Value |
Unit |
Hfe @ Ic=10 µA |
8 |
- |
Bvceo @ Ic=1 µA |
-63 |
V |
Bvces @ Ic=1 µA |
-67 |
V |
Icmax |
250 |
µA |
Vertical Medium-Voltage “High Gain” PNP Transistor: VPHB (Parameter, E_area=0.64µm²) |
Typical
Value |
Unit |
Hfe @ Ic=100 nA |
115 |
- |
|Bvceo|@ Ic=1 µA |
>80 |
V |
|Bvces|@ Ic=1 µA |
>100 |
V |
Icmax |
250 |
µA |
Medium Voltage NPN (Parameter, E_area=16 µm²) |
Typical
Value |
Unit |
Hfe max |
120 |
- |
Bvceo @ Ic=1 µA |
23 |
V |
Bvces @ Ic=1 µA |
>80 |
V |
|VEarly| |
>70 |
V |
Capacitors (Parameter @ 25°C)
Type (Maximum Voltage) |
Typical
Value |
Unit |
Metal2/Metal2.5 Plate: MIMC (3.6 V) |
1.5 |
fF/µm² |
Metal1/Metal3 Plate (80 V) |
0.1 |
fF/µm² |
Poly/Metal3 Plate (80 V) |
0.14 |
fF/µm² |
Metal1/Metal3 Bar (80 V) |
0.26 |
aF/µm/
finger |
Poly/Metal3 Bar (80 V) |
0.33 |
aF/µm/
finger |
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|
High-Voltage Transistors
Floating NMOS @ 80 V |
Typical
Value |
Unit |
Vt (10/0.35, linear extrapolated) |
0.59 |
V |
Vmax=Vfloat to P-substrate |
80 |
V |
Vmax=Vbd |
3.6 |
V |
IDS (10/0.35, Vds=Vgs=3.3 V) |
530 |
µA/µm |
Floating PMOS @ 80 V |
Vt (10/0.35, linear extrapolated) |
-0.57 |
V |
Vmax=Vfloat to P-substrate |
80 |
V |
Vmax=Vbd |
-3.6 |
V |
IDS (10/0.35, Vds=Vgs=3.3 V) |
-250 |
µA/µm |
Floating NDMOS for Switching Application: VFNDM80 |
Vt |
0.54 |
V |
Vmax=Vbd (higher if self protected) |
70 |
V |
Vgsmax (full lifetime) |
3.6 |
V |
Ids (Vds=40, Vgs=1.5 V) |
100 |
µA/µm |
Ron*Area (block of 16 fingers) |
Without isolation |
180 |
mΩ*mm² |
With isolation |
260 |
mΩ*mm² |
Floating NDMOS for Analog Application: VFNDM80A |
Vt |
0.56 |
V |
Vmax=Vbd (higher if self protected) |
70 |
V |
Vgsmax (full lifetime) |
3.6 |
V |
Ids (Vds=40, Vgs=1.5 V) |
70 |
µA/µm |
Ron*Area (block of 16 fingers) |
Without isolation |
250 |
mΩ*mm² |
With isolation |
325 |
mΩ*mm² |
Floating Medium Voltage NDMOS |
Vt |
0.58 |
V |
Vmax=Vbd |
14 |
V |
Vgsmax (full lifetime) |
3.6 |
V |
Ids (Vds=10 V, Vgs=+3.3 V) |
300 |
µA/µm |
Ron*Area |
31 |
mΩ*mm² |
Floating HV PMOS: LFPDM80 |
Vt (W=40mm) |
-0.56 |
V |
Vmax=Vbd |
-70 |
V |
Vgsmax (full lifetime) |
-3.6 |
V |
Ids (Vds=-40V, Vgs=-1.5 V) |
18.5 |
µA/µm |
Ron*Area |
280 |
mΩ*mm² |
Floating PDMOS: LFPDMS |
Vt |
-0.56 |
V |
Vmax=Vbd |
-5.5 |
V |
Vgsmax |
-3.6 |
V |
Ids (Vds=-5 V, Vgs=-3.3 V) |
96 |
µA/µm |
Resistors (Parameter @ 25°C)
Resistor Type |
Typical
Value |
Unit |
High-Resistance Poly: HIPO |
975 |
Ω/square |
Salicided P+ Poly: LOPOR |
2.4 |
Ω/square |
Unsalicided P+ Poly: PPOLR |
240 |
Ω/square |
Unsalicided P+ in Mwell |
64 |
Ω/square |
Unsalicided N+ Poly: NPOLR |
292 |
Ω/square |
Unsalicided N+ in Pwell |
47.5 |
Ω/square |
Nwell under FOX (field oxide) |
958 |
Ω/square |
Nwell in AA (active area) |
800 |
Ω/square |
Pwell in AA (active area) |
1755 |
Ω/square |
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Libraries |
Standard Cell |
Ultra High Density Core Cell |
pn sum: 2.0 |
Area of 2-input nand (na21): 38.88 µm² |
Gate density (na21 @ 100% utilization): 25.72 k gates/mm² |
Scan Flop density (scan flops @100% utilization): 3.215 k ff/mm² |
Average power (@ 3.3 V): 0.2929 µW/MHz/gate |
Standard I/O |
Fat Pad I/O Library (for core limited designs) |
190.80 µm min in-line pad pitch |
203.40 µm pad height |
Tall Pad I/O Library (for pad limited designs) |
97.20 µm min in-line pad pitch |
374.40 µm pad height |
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Memory Options |
RAM |
Synchronous High Speed/High Temp Single Port SRAM |
Minimum: 16 words x 2 bits |
Maximum: 128 k bits
(ie: 16 k words x 8 bits, 8 k words x 16 bits, …) |
Synchronous High Speed/High Temp Dual Port SRAM |
Minimum: 16 words x 2 bits |
Maximum: 128 k bits
(ie: 16 k words x 8 bits, 8 k words x 16 bits, …) |
Low Power Synchronous SRAM |
Minimum: 64 words x 4 bits |
Maximum: 128 k bits
(ie: 16 k words x 8 bits, 8 k words x 16 bits, …) |
ROM |
Synchronous High Speed/High Temp Diffusion ROM |
Minimum: 256 words x 4 bits |
Maximum: 512 k bits
(ie: 64 k words x 8 bits, 32 k words x 16 bits, …) |
Low Power Synchronous Via Programmable ROM |
Minimum: 256 words x 4 bits |
Maximum: 512 k bits
(ie: 64 k words x 8 bits, 32 k words x 16 bits, …) |
Non-Volatile Memory |
OTP – One Time Programmable |
Fuse: Zener Diode optimized for low power zapping |
Both Serial and Parallel Output Capability |
In field programming available |
Vector: Up to 320 bits |
FLASH |
Differential Bit Cell (Redundancy for High Reliability) |
Sectore and multiple sector erase in 0.5s |
Page program in 20 µs |
Automotive qualification AEC-Q100 |
64K Byte storage |
Internal Charge Pump provided |
Memory Failure Rate: <1ppm with ECC |
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CAD Tool Compatibility |
Digital Design |
Synopsys Design Compiler |
Cadence Verilog |
Analog Design |
Cadence DFII (4.4.6) |
Spectre |
Place and Route |
Synopsys Apollo |
Cadence Silicon Ensemble |
Physical Verification |
Mentor Graphics Calibre |
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For more information please contact your local sales support at www.onsemi.com |