feedback
评价本网页


需要帮助?


NB3N502DEVB: PLL Clock Multiplier Evaluation Board

评估/开发工具简介
The NB3N502 Evaluation Board was designed to provide a flexible and convenient platform to quickly evaluate, characterize and verify the performance and operation of the NB3N502 PLL Clock Multiplier. The NB3N502 is a clock multiplier device that generates a low jitter, TTL/CMOS level output clock which is a precise multiple of the external input reference clock signal source. The user's manual provides detailed information on the board's contents, layout and use, and it should be used in conjunction with the NB3N502 data sheet which contains full technical details on device specifications and operation.
特性和应用

特性

  • Fully Assembled Evaluation Board
  • Accommodates the Electrical Characterization of the NB3N502 in the SOIC-8 Package
  • Supports the Use of a 5 MHz to 27 MHz Through-hole or Surface Mount Crystal
  • SMA Connectors are Provided for Auxiliary Input and Output Interfaces
  • Incorporates Onboard Slide Switch Controlled Multiplier Select Pins, Minimizing Excess Cabling
评估/开发工具信息
产品 状况 Compliance 简短说明 所用产品 行动
NB3N502DEVB Active
PLL Clock Multiplier Evaluation Board NB3N502DGNB3N502DR2G
Avnet (2015-07-09) : 2
技术文档
类型 文档标题 文档编号/大小 修订号
Eval Board: Manual NB3N502DEVB Evaluation Board User's Manual EVBUM2064/D - 247.0 KB  1 
之前浏览的产品
清除列表