数据表
|
按文档类型:
|
|
- 或 - |
|
|
|
数据表 用于
ECLinPS MAX
(显示所有)
页面尺寸:
1 - 22 of 22
[
1
]
|
|
|
|
|
| 1.8V / 2.5V Differential 4:1 Mux w/Input Equalizer to1:2 CML Clock/Data Fanout |
NB6VQ572M/D (1260.0kB) |
0 |
|
| 2.5 V / 3.3V Any Differential Clock IN to Differential LVPECL OUT Dual Bank 1/2/4/8 and 2/4/8/16 Divider |
NB6L239/D (141.0kB) |
6 |
|
| 2.5 V 1:2 AnyLevel Input to LVDS Fanout Buffer / Translator |
NB6L11S/D (225kB) |
9 |
Nov, 2014 |
| 2.5 V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer |
NB6L14S/D (235.0kB) |
2 |
|
| 2.5 V/3.3 V 3.0 GHz Differential 1:4 CML Fanout Buffer |
NB6L14M/D (103.0kB) |
3 |
|
| 2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer |
NB6L14/D (194.0kB) |
5 |
|
| 2.5V / 3.3V 1:2 Differential CML Fanout Buffer |
NB6L11M/D (151.0kB) |
4 |
|
| 2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buffer |
NB6L611/D (189.0kB) |
4 |
|
| 2.5V / 3.3V Differential 2 X 2 Crosspoint Switch with LVPECL Outputs |
NB6L72/D (134.0kB) |
4 |
|
| 2.5V / 3.3V Differential 4:1 Mux to 1:2 CML Clock/Data Fanout / Translator |
NB6L572M/D (156.0kB) |
1 |
|
| 2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator |
NB6LQ572M/D (817.0kB) |
0 |
|
| 2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 LVPECL Clock/Data Fanout / Translator |
NB6LQ572/D (182.0kB) |
0 |
|
| 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs |
NB6L295M/D (193.0kB) |
5 |
|
| 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs |
NB6L295/D (192.0kB) |
4 |
|
| 2.5V 5GHz / 6.5Gbps Differential Input to 1.8V /2.5V 1:4 CML Clock / Data Fanout Buffer w/ Selectable Input Equalizer |
NB6HQ14M/D (1259.0kB) |
0 |
|
| 2x2 Crosspoint Switch, 2.5 V / 3.3 V Differential, with CML Outputs |
NB6L72M/D (129.0kB) |
3 |
|
| 3.3 V 1:2 AnyLevel Input to LVDS Fanout Buffer / Translator |
NB6N11S/D (223kB) |
7 |
Nov, 2014 |
| 3.3 V 1:4 AnyLevel Input to LVDS Fanout Buffer / Translator |
NB6N14S/D (273.0kB) |
8 |
|
| 3.3V, 3.0 GHz Any Differential Clock IN to LVDS OUT Div 1/2/4/8, Div 2/4/8/16 Clock Divider |
NB6N239S/D (141.0kB) |
6 |
|
| Clock / Data Multiplexer, 2.5 V / 3.3 V Dual 2:1 Differential, with LVPECL Outputs |
NB6L56/D (133.0kB) |
0 |
|
| Clock or Data Fanout Buffer / Translator, 2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 |
NB6L11/D (322.0kB) |
9 |
|
| Clock or Data Receiver / Driver / Translator Buffer, 2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL |
NB6L16/D (235.0kB) |
8 |
|
|
|
|