The NB3N3020DTG is a high precision, low phase noise selectable clock multiplier. The device takes a 5 - 27 MHz fundamental mode parallel resonant crystal or a 2 - 210 MHz LVCMOS single ended clock source and generates a differential LVPECL output and a single ended LVCMOS/LVTTL output at a selectable clock output frequency which is a multiple of the input clock frequency. Three tri-level (Low, Mid, High) LVCMOS/LVTTL single ended select pins set one of 26 possible clock multipliers. An LVCMOS/LVTTL output enable (OE) tri-states clock outputs when low. This device is housed in 5 mm x 4.4 mm narrow body TSSOP-16 pin package.
The NB3N3020DTGEVB Evaluation board is designed to provide a flexible and convenient platform to quickly program, evaluate and verify the performance and operation of the NB3N3020DTG TSSOP-16 device under test: With the device removed, this NB3N5573DTGEVB Evaluation board is designed to accept a 16 Lead TSSOP Socket to permit use as an insertion test fixture.
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NB3N3020DTGEVB_BOM
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Eval Board: BOM
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Eval Board: BOM
March 12, 2025
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NB3N3020DTGEVB_SCHEMATIC
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Eval Board: Schematic
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Eval Board: Schematic
March 12, 2025
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NB3N3020DTGEVB_TEST_PROCEDURE
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Eval Board: Test Procedure
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Eval Board: Test Procedure
April 01, 2026
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NB3N3020DTGEVB_GERBER
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Eval Board: Gerber
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Eval Board: Gerber
March 12, 2025
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EVBUM2063/D
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Eval Board: Manual
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Eval Board: Manual
November 01, 2019
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