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Audio ASSP | LC72711LW
概览
LC72711LW 是一个数据解调器集成电路，用于接收以 DARC 格式进行移动接收的 FM 多路广播。该集成电路包括一个片上带通滤波器，用于从 FM 基带信号中提取 DARC 信号。此外，由于该集成电路支持所有 IT-R 建议的 FM 多路复用帧结构（方法A、A、B 和 C），因此它是提供 FM 多路复用接收的全球市场无线电的最佳选择。LC72711LW 支持并行和“计算机控制总线”串行 CPU 接口。
- Adjustment-free 76 kHz SCF bandpass filter
- Supports all FM multiplex frame structures under CPU control.
- MSK delay detection system based on a 1T delay.
- Error correction function based on a 2T delay (in the MSK detection stage)
- Digital PLL based clock regeneration function
- Shift-register 1T and 2T delay circuits
- Block and frame synchronization detection circuits
- Functions for setting the number of allowable BIC errors and the number of synchronization protection operations.
- Error correction using (272, 190) codes
- Built-in layer 4 CRC code checking circuit
- On-chip frame memory and memory control circuit for vertical correction
- 7.2 MHz crystal oscillator circuit
- Two power saving modes: STNBY and EC STOP
- Applications can use either a parallel CPU interface (DMA) or a 'computer control bus' serial interface.
- Supply voltage: 2.7 to 3.6 V
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