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此 P 沟道逻辑电平增强型场效应晶体管是使用高单元密度的 DMOS 专属技术生产的。这种极高密度工艺特别适用于最大程度降低导通电阻。此器件是专为在低压应用中替代数字晶体管而设计的。因为无需偏置电阻,所以此单 P 沟道 FET 可以替代若干具有各种偏置电阻的数字晶体管,如 DTCx 和 DCDx 系列。
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CAD Models
Compliance
Package Type
Case Outline
MSL Type
MSL Temp (°C)
Container Type
Container Qty.
ON Target
Channel Polarity
Silicon Family
Package Name
Type
Gate Level
Wide SOA Mosfets
Configuration
OPN in older Technology
V(BR)DSS Min (V)
RDS(on) Max @ VGS = 10 V (mΩ)
VGS Max (V)
Vgs(th) Max (V)
Id Max (A)
PD Max (W)
RDS(on) Max @ VGS = 2.5 V (mΩ)
RDS(on) Max @ VGS = 4.5 V (mΩ)
Qg Typ @ VGS = 4.5 V (nC)
Qg Typ @ VGS = 10 V (nC)
Ciss Typ (pF)
Qgd Typ @ VGS = 4.5 V (nC)
Qrr Typ (nC)
Coss Typ (pF)
Crss Typ (pF)
Reference Price
FDV302P
Pb
A
H
P
SOT-23 (TO-236) 2.90x1.30x1.00, 1.90P
1
260
REEL
3000
N
P-Channel
PowerTrench® T1
SOT-23-3/5
Small Signal
Logic
0
Single
0
-25
-
-8
-1.5
-0.12
0.35
NA
13000
0.22
0.22
NA
-
-
-
-
Price N/A
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可靠性数据
Die Related Summary Data
Device: FDV302P
Equivalent to wafer fab process: TP
产品技术
产品技术
等效器件小时
平均故障间隔时间/平均无故障时间(按小时计算)
FITS
TP
8
738717284
More Details
Re-calculate Data
Data is based on the following assumptions.
Note: The temperature and confidence level may be adjusted to your requirements.
Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)