Arithmetic Logic Functions | MC14526B
概览
The MC14526B binary counter is constructed with MOS P-channel and N-channel enhancement mode devices in a monolithic structure. This device is presettable, cascadable, synchronous down counter with a decoded "0" state output for divide-by-N applications. In single stage applications the "0" output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide-by-N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock.
This complementary MOS counter can be used in frequency synthesizers, phase-locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity.
- Supply Voltage Range = 3.0 Vdc to 18 Vdc
- Logic Edge-Clocked Design - Incremented on Positive Transition of Clock or Negative Transition of Inhibit
- Asynchronous Preset Enable
- Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range
- Pb-Free Packages are Available
产品参数及购买信息
搜寻
Close Search
产品:
2
分享
排序方式
产品系列:
┗
可订购器件:
2
Show More
1-25 of 25
Products per page
Jump to :
1
支持服务
联系安森美销售团队获得支持，查询或者对比产品细节。
联系销售
