D Flip-Flops and JK Flip-Flops | NLSF1174
Hex D Flip-Flop with Common Clock and Reset
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概览
This device consists of six flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-tohigh transition; of the Clock input. Reset is asynchronous and active low. All inputs/outputs are standard CMOS compatible.
- Output Drive Compatibility: 10 LSTTL Loads
- Outpus Directly Interface to CMOS
- Operation Voltage Range: 2 to 6 V
- Low Input Current: 1.0 µ A
- MSL Level 1
- Chip Complexity: 162 FET
- Pb-Free Package is Available
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