Arithmetic Functions | MC100EP33

3.3 V / 5.0 V ECL ÷·4 分频器

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MC10/100EP33 是一款集成式 4 分频分频器。差分时钟输入。仅为此器件提供 VBB 引脚，即内部产生的供应电压。对于单端输入情况，未使用的差分输入将作为开关参考电压联接 VBB。VBB 还可将 AC 耦合输入重偏置。使用时，通过一个 0.01 uF 电容将 VBB 和 VCC 去耦合，并限制电流源或接收 0.5mA 的电流。不使用时，VBB 应保持开路。重置引脚是异步的，在上升边进行断言。通电时，内部触发器将达到随机状态；重置可对系统中的多个 EP33 进行同步。100 系列包含温度补偿。

  • Phase Lock Loops

  • 320ps Propagation Delay
  • Maximum Frequency > 4 GHz Typical
  • PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Q Output will default LOW with inputs open or at VEE
  • VBB Output
  • Pb-Free Packages are Available

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MC100EP33DTG

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Pb

A

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TSSOP-8

948R-02

3

260

TUBE

100

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CML

ECL

ECL

5

4000

0.38

200

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MC100EP33DTR2G

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Pb

A

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TSSOP-8

948R-02

3

260

REEL

2500

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ECL

5

4000

0.38

200

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MC100EP33MNR4G

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Pb

A

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DFN-8

506AA

1

260

REEL

1000

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ECL

5

4000

0.38

200

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可靠性数据

Die Related Summary Data

Device: MC100EP33DTG

Equivalent to wafer fab process: MOSAIC

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等效器件小时

平均故障间隔时间/平均无故障时间（按小时计算）

FITS

MOSAIC

0

476668904

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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