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MC100EP210S 是一款低歪曲率 1:5 双路差分驱动器,在设计时考虑到了 LVDS 时钟分配。LVDS 或 LVPECL 输入信号为差分信号,并且信号被分配为五个相同的差分 LVDS 输出。EP210S 可特别保证低输出-输出歪曲率。优化的设计、布局和处理最大程度降低了器件内和器件到器件的歪曲率。整个输入提供两个内部 50 欧姆电阻。对于 LVDS 输入,应断开 VTA 和 VTB 引脚的连接。对于 LVPECL 输入,应将 VTA 和 VTB 引脚连接至 VTT(VCC-2.0 V)电源。设计人员可充分利用 EP210S 的性能,在底板或主板上分配低歪曲率 LVDS 时钟。在无信号条件下,应对差分输入进行特别考虑以防止不稳定。
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Input Level
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VCC Typ (V)
tJitterRMS Typ (ps)
tskew(o-o) Max (ps)
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Reference Price
MC100EP210SFAG
Active
Pb
A
H
P
LQFP-32
2
260
JTRAY
250
Y
Buffer
2
1:5
CML
ECL
LVDS
LVDS
2.5
0.2
25
0.55
200
1000
-
Price N/A
More Details
MC100EP210SFAR2G
Active
Pb
A
H
P
LQFP-32
2
260
REEL
2000
Y
Buffer
2
1:5
CML
ECL
LVDS
LVDS
2.5
0.2
25
0.55
200
1000
-
Price N/A
More Details
MC100EP210SMNG
Active
Pb
A
H
P
QFN-32
1
260
TUBE
74
Y
Buffer
2
1:5
CML
ECL
LVDS
LVDS
2.5
0.2
25
0.55
200
1000
-
Price N/A
More Details
MC100EP210SMNR4G
Active
Pb
A
H
P
QFN-32
1
260
REEL
1000
Y
Buffer
2
1:5
CML
ECL
LVDS
LVDS
2.5
0.2
25
0.55
200
1000
-
Price N/A
More Details
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可靠性数据
Die Related Summary Data
Device: MC100EP210SFAG
Equivalent to wafer fab process: MOSAIC
产品技术
产品技术
等效器件小时
平均故障间隔时间/平均无故障时间(按小时计算)
FITS
MOSAIC
0
476668904
More Details
Re-calculate Data
Data is based on the following assumptions.
Note: The temperature and confidence level may be adjusted to your requirements.
Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)