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The NB3L202K is a differential 1:2 Clock fanout buffer withHigh−speed Current Steering Logic (HCSL) outputs. Inputs candirectly accept differential LVPECL, LVDS, and HCSL signals.Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels areaccepted with a proper external Vth reference supply per Figures 4and 6. The input signal will be translated to HCSL and provides twoidentical copies operating up to 350 MHz.The NB3L202K is optimized for ultra−low phase noise, propagationdelay variation and low output–to–output skew, and is DB200Hcompliant. As such, system designers can take advantage of theNB3L202K’s performance to distribute low skew clocks across thebackplane or the motherboard making it ideal for Clock and Datadistribution applications such as PCI Express, FBDIMM, Networking,Mobile Computing, Gigabit Ethernet, etc.Output drive current is set by connecting a 475 resistor fromIREF (Pin 10) to GND per Figure 11. Outputs can also interface toLVDS receivers when terminated per Figure 12.
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VCC Typ (V)
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Reference Price
NB3L202KMNG
Active
Pb
A
H
P
QFN-16
1
260
TUBE
123
Y
Buffer
1
1:2
HCSL
LVDS
LVPECL
HCSL
3.3
0.046
20
1
700
350
-
Price N/A
More Details
NB3L202KMNTXG
Active
Pb
A
H
P
QFN-16
1
260
REEL
3000
Y
Buffer
1
1:2
HCSL
LVDS
HCSL
3.3
0.046
20
1
700
350
-
Price N/A
More Details
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可靠性数据
Die Related Summary Data
Device: NB3L202KMNG
Equivalent to wafer fab process: ONC18
产品技术
产品技术
等效器件小时
平均故障间隔时间/平均无故障时间(按小时计算)
FITS
ONC18
2
6465777234
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Data is based on the following assumptions.
Note: The temperature and confidence level may be adjusted to your requirements.
Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)