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The NB3N853531E is a low skew 3.3 V supply 2:1:4 clock distribution fanout buffer. An input MUX selects either a Fundamental Parallel Mode Crystal or a LVCMOS/LVTTL Clock by using the CLK_SEL pin (HIGH for Crystal, LOW for Clock) with LVCMOS / LVTTL levels. The single ended CLK input is translated to four LVPECL Outputs. Using the crystal input, the NB3N853531E can be a Clock Generator. A CLK_EN pin can enable or disable the outputs synchronously to eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable outputs, LOW to disable output).
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VCC Typ (V)
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tskew(o-o) Max (ps)
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fmaxData Typ (Mbps)
Reference Price
NB3N853531EDTR2G
Active
Pb
A
H
P
TSSOP-20
1
260
REEL
2500
Y
Buffer
1
2:1:4
Crystal
LVCMOS
LVTTL
LVPECL
3.3
0.053
30
-
600
-
~NA~
Price N/A
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可靠性数据
Die Related Summary Data
Device: NB3N853531EDTR2G
Equivalent to wafer fab process: ONC25
产品技术
产品技术
等效器件小时
平均故障间隔时间/平均无故障时间(按小时计算)
FITS
ONC25
1
2712519294
More Details
Re-calculate Data
Data is based on the following assumptions.
Note: The temperature and confidence level may be adjusted to your requirements.
Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)