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The MC10/100EP51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices.
The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLKbar input will be biased at VCC / 2.
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MSL Temp (°C)
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Container Qty.
ON Target
Type
Bits
Input Level
Output Level
VCC Typ (V)
tJitter Typ (ps)
tpd Typ (ns)
tsu Min (ns)
th Min (ns)
trec Typ (ns)
tR & tF Max (ps)
fToggle Typ (MHz)
Reference Price
MC10EP51DR2G
Active
Pb
A
H
P
SOIC-8
1
260
REEL
2500
Y
D-Type
1
CML
ECL
ECL
5
0.2
0.375
0.1
0.1
0.15
170
3000
Price N/A
More Details
MC10EP51DTG
Active
Pb
A
H
P
TSSOP-8
3
260
TUBE
100
Y
D-Type
1
CML
ECL
ECL
5
0.2
0.375
0.1
0.1
0.15
170
3000
Price N/A
More Details
MC10EP51MNTAG
Active
Pb
A
H
P
DFN-8
1
260
REEL
1000
Y
D-Type
1
CML
ECL
ECL
5
0.2
0.375
0.1
0.1
0.15
170
3000
Price N/A
More Details
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可靠性数据
Die Related Summary Data
Device: MC10EP51DR2G
Equivalent to wafer fab process: MOSAIC
产品技术
产品技术
等效器件小时
平均故障间隔时间/平均无故障时间(按小时计算)
FITS
MOSAIC
0
476668904
More Details
Re-calculate Data
Data is based on the following assumptions.
Note: The temperature and confidence level may be adjusted to your requirements.
Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)