Skew Management | MC100EP196B

3.3 V ECL 可编程延迟芯片，带 FTUNE

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概览

MC100EP196B 是一款可编程延迟芯片 (PDC)，主要用于时钟去歪曲和计时调整。它提供了差分 NECL/PECL 输入转换的可变延迟。它与 EP195 结构相似，但使用 FTUNE 引脚增加了延迟中的进一步微调功能。FTUNE 输入采用从 VCC 到 VEE 的模拟电压来微调输出延迟，其范围为 0 到 60 ps。延迟部分由一个可编程的门极和多工器矩阵组成，如图 2 逻辑图所示。 EP196B 延迟增量的可数字选择分辨率约为 10 ps， 净范围最高 10.4 ns。所需延迟由 10 个数据选择输入 D(9:0) 值选择，由 LEN（引脚 10）控制。LEN 上的低电平可实现 D(9:0) 确定的实时延迟值的透明加载模式。LEN 上的低电平-高电平转换将针对 D(10:0) 中的任何后续变化锁定并保持现有电流值。表 6 和图 3 中显示了与 D0 (LSB) 至 D9 (MSB) 相关联的各种抽头数的恰当延迟值。

  • Automated Test Equipment (ATE)
  • Maximum Input Clock Frequency >1.2 GHz Typical
  • Programmable Range: 0 ns to 10 ns
  • Delay Range: 2.2 ns to 12.4 ns
  • 10 ps Increments
  • Linearity 40 ps max
  • PECL Mode Operating Range:VCC = 3.0 V to 3.6 V with VEE = 0 V
  • NECL Mode Operating Range:VCC = 0 V with VEE = 3.0 V to 3.6 V
  • IN/INb Inputs Accept LVPECL, LVNECL, LVDS Levels
  • A Logic High on the ENb Pin Will Force Q to Logic Low
  • D10:0 Can Select Either LVPECL, LVCMOS, or LVTTL Input Levels
  • VBB Output Reference Voltage

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CAD Models

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Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Input Level

Output Level

VCC Typ (V)

fMax Typ (MHz)

td(prog) Min (ns)

td(prog) Max (ns)

td(step) Typ (ps)

tJitter Typ (ps)

tR & tF Max (ps)

Reference Price

MC100EP196BFAG

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Active

CAD Model

Pb

A

H

P

LQFP-32

561AB

2

260

JTRAY

250

N

LVDS

ECL

3.3

1200

8.95

12.11

11

2.6

210

$11.733

More Details

MC100EP196BMNG

Contact Sales

Active

CAD Model

Pb

A

H

P

QFN-32

488AM

2

260

TUBE

74

Y

LVDS

ECL

3.3

1200

8.95

12.11

11

2.6

210

Price N/A

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