The MC100LVEL90 is a triple ECL to LVPECL translator. The device receives either -3.3 V or -5 V differential ECL signals, determined by the VEE supply level, and translates them to +3.3 V differential LVPECL output signals.
To accomplish the level translation, the LVEL90 requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GND pins, as expected, are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.015F capacitors.
Under open input conditions, the Dbar input will be biased at VEE/2 and the D input will be pulled to VEE . This condition will force the Q output to a LOW, ensuring stability.
The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. BB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
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Die Related Summary Data
Device: MC100LVEL90DWR2G
Equivalent to wafer fab process: MOSAIC
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等效器件小时
平均故障间隔时间/平均无故障时间(按小时计算)
FITS
MOSAIC
0
476668904
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Data is based on the following assumptions.
Note: The temperature and confidence level may be adjusted to your requirements.
Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)