PLL Clock Generators | NB3N3002

时钟生成器，PureEdge™，晶体 - 25 MHz，100 MHz，125 MHz，200 MHz 和 3.3 V，带差分 HCSL 输出

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概览

NB3N3002 是一款高精确度、低相位干扰时钟生成器，支持 PCI Express 和以太网要求。该器件采用 25 MHz 基础模式并行谐振晶体，以 25 MHz、100MHz、125 MHz 或 200 MHz 时钟频率生成差分 HCSL 输出。此器件采用 5.0 mm x 4.4 mm 窄体 TSSOP 16 引脚封装。

  • Gigabit Ethernet
  • FBDIMM
  • PCIe Gen 1, Gen 2, Gen 3 and Gen 4

  • Servers
  • Networking Equipment

  • Typical TIE RMS jitter of 2.5 ps
  • Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
  • HCSL Differential Output
  • Operating Range 3.3 V 5%
  • Industrial Temperature Range -40C to +85C
  • PCIe Clock Generation Gen 1, Gen 2, Gen 3, Gen 4

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Output Level

VS Typ (V)

fin Typ (MHz)

fout Typ (MHz)

tJitter(Cy-Cy) Typ (ps)

tJitter(Period) Typ (ps)

tJitter(Φ) Typ (ps)

tR & tF Typ (ps)

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NB3N3002DTG

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CAD Model

Pb

A

H

P

TSSOP-16

948F-01

1

260

TUBE

96

Y

CMOS

TTL

HCSL

3.465

25

25

2

1.5

0.25

340

700

-40

85

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NB3N3002DTR2G

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CAD Model

Pb

A

H

P

TSSOP-16

948F-01

1

260

REEL

2500

Y

CMOS

TTL

HCSL

3.465

25

25

2

1.5

0.25

340

700

-40

85

Price N/A

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可靠性数据

Die Related Summary Data

Device: NB3N3002DTG

Equivalent to wafer fab process: CMOS SUB

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等效器件小时

平均故障间隔时间/平均无故障时间（按小时计算）

FITS

CMOS SUB

2

920154574

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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