PLL Clock Generators | NB3N3020

时钟乘法器，LVPECL / LVCMOS，可编程，3.3 V

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NB3N3020 是一款高精度、低相位干扰可选择时钟乘法器。该器件采用 5.0-27 MHz 基础模式并联谐振晶体，或 2.0-210 MHz LVCMOS 单端时钟源，以可选择的时钟输出频率生成差分 LVPECL 输出和单端 LVCMOS/LVTTL 输出，该频率为输入时钟频率的倍数。三个三电平 LVCMOS/LVTTL 单端选择引脚设置 26 个可能时钟乘法器中的一个。LVCMOS/LVTTL 输出启用 (OE) 引脚在低电平时会对时钟输出进行三态设置。该器件采用 5.0 x 4.4 mm TSSOP-16 封装。

  • Routers, Consumer Networking, Set Top Box, Digital TV, Home Gateways, Servers, Consumer Electronics

  • Servers, Routers, DTV, Set Top Box

  • Period Jitter RMS of 5.0 ps
  • 1 LV-PECL Differential Output and 1 LVMOS/LVTTL single ended output
  • Selectable Clock Multiplier
  • Operating Range - 3.3V +/- 10%
  • Industrial Temperature Range -40C to +85C

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MSL Temp (°C)

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Input Level

Output Level

VS Typ (V)

fin Typ (MHz)

fout Typ (MHz)

tJitter(Cy-Cy) Typ (ps)

tJitter(Period) Typ (ps)

tJitter(Φ) Typ (ps)

tR & tF Typ (ps)

tR & tF Max (ps)

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NB3N3020DTG

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CAD Model

Pb

A

H

P

TSSOP-16

948F-01

1

260

TUBE

96

Y

CML

CMOS

ECL

ECL

TTL

3.3

5-27

8-210

20

15

-

340

700

-40

85

Price N/A

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NB3N3020DTR2G

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Active

CAD Model

Pb

A

H

P

TSSOP-16

948F-01

1

260

REEL

2500

Y

CML

CMOS

ECL

ECL

TTL

3.3

5-27

8-210

20

15

-

340

700

-40

85

Price N/A

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可靠性数据

Die Related Summary Data

Device: NB3N3020DTG

Equivalent to wafer fab process: CMOS SUB

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等效器件小时

平均故障间隔时间/平均无故障时间（按小时计算）

FITS

CMOS SUB

2

920154574

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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