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PLL Clock Generators | NB3N51044
概览
NB3N51044 是一款精密低相位干扰时钟产生器，支持 PCI Express 和 sRIO 时钟要求。该器件接受 25 MHz 基础模式并联谐振晶体或 25 MHz 单端参考时钟信号，并根据频率选择输入 F_SEL 生成四个 100 MHz 或 125 MHz 时钟频率的 HCSL / LVDS 差分输出。NB3N51044 可配置为使用 BYPASS 从信号路径旁通 PLL，并通过分频器网络提供输出频率。所有时钟输出都可以通过硬件输入引脚 OE 单独启用/禁用。此外，可以使用主重置输入引脚 MR_OE＃来重置器件。
- Networking
- Consumer
- Computing and Peripherals
- Industrial Equipment
- PCIe Clock Generation Gen 1, Gen 2, Gen 3 and Gen 4
- Switch and Router
- Set Top Box, LCD TV
- Servers, Desktop Computers
- Automated Test Equipment
- Output frequency selection of 100 MHz or 125 MHz
- Typical Phase Jitter @ 125 MHz (integrated 1.875 MHz to 20 MHz): 0.2 ps
- Typical Cycle-cycle Jitter @ 100 MHz (10k cycles): 20 ps
- Uses 25 MHz Fundamental Crystal or Reference Clock Input
- Four Low Skew HCSL or LVDS Outputs
- Individual OE Tri-states Output
- Master Reset and BYPASS modes
- PCIe Gen 1, Gen 2, Gen 3, Gen 4 jitter Compliant
- Operating Supply Voltage Range 3.3 V ± 5%
- Industrial Temperature Range-40°C to +85°C
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NB3N51044DTR2G
Active
Pb
A
H
P
TSSOP-28
1
260
REEL
2500
Y
CMOS
Crystal
HCSL
LVDS
3.3
25
125
20
-
0.4
-
-
-40
85
Price N/A
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