Zero Delay Buffers | NB3N1900K
概览
NB3N1900K 差分时钟缓冲器适用于结合符合 PCIe 标准的源时钟合成器来为多个代理提供点对点时钟。该器件能够为 Intel® QuickPath Interconnect (Intel QPI & UPI)、PCIe Gen1、Gen2、Gen3、Gen4 分发参考时钟。NB3N1900K 内部 PLL 支持 100 MHz 和 133 MHz 频率运行。NB3N1900K 支持 HCSL 输出电平。
- Industrial
- Networking
- Computing
- Consumer
- PCIe Gen 1, Gen 2, Gen 3, Gen 4
- Desktop
- Notebook
- Switchers/Routers
- Servers
- Set Top Box
- Automated Test Equipment
- Fixed Feedback Path for Lowest Input−to−Output Delay
- Eight Dedicated OE# Pins for Hardware Control of Outputs
- PLL Bypass Configurable for PLL or Fanout Operation
- Selectable PLL Bandwidth
- Spread Spectrum Compatible: Tracks Input Clock Spreading for LowEMI
- SMBus Programmable Configurations
- 100 MHz and 133 MHz PLL Mode to Meet the Next Generation PCIe Gen2 / Gen 3 /Gen 4 and Intel QPI & UPI Phase Jitter
- 2 Tri−Level Addresses Selection (Nine SMBUS Addresses)
- Cycle−to−Cycle Jitter: < 50 ps
- Output−to−Output Skew: < 65 ps
- Input−to−Output Delay: Fixed at 0 ps
- Input−to−Output Delay Variation: < 50 ps
- Phase Jitter: PCIe Gen3 < 1 ps rms
- Phase Jitter: PCIe Gen4 < 0.5 ps rms
- Phase Jitter: QPI 9.6GB/s < 0.2 ps rms
- QFN 72−pin Package, 10 mm x 10 mm
- These are Pb−Free Devices
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