Zero Delay Buffers | NB3W1200L
概览
The NB3N1200K and NB3W1200L differential clock buffers areDB1200Z and DB1200ZL compliant and are designed to work inconjunction with a PCIe compliant source clock synthesizer to providepoint−to−point clocks to multiple agents. The device is capable ofdistributing the reference clocks for Intel® QuickPath Interconnect(Intel QPI & UPI), PCIe Gen1/Gen2/Gen3/Gen4, SAS, SATA, and Intel ScalableMemory Interconnect (Intel SMI) applications. The VCO of thedevice is optimized to support 100 MHz and 133 MHz frequencyoperation. The NB3N1200K and NB3W1200L utilizepseudo−external feedback topology to achieve low input−to outputdelay variation. The NB3N1200K is configured with the HCSL buffertype, while the NB3W1200L is configured with the low−powerNMOS Push−Pull buffer type.
- Industrial
- Networking
- Computing
- Consumer
- Desktop
- Notebook
- Switchers/Routers
- Servers
- Set Top Box
- Automated Test Equipment
- 12 Differential Clock Output Pairs @ 0.7 V
- Low−Power NMOS Push−Pull Compatible Outputs for NB3W1200L
- Optimized 100 MHz and 133 MHz Operating Frequencies to Meet The Next Generation PCIe Gen 2/Gen 3/ Gen 4 and Intel QPI & UPI Phase Jitter
- DB1200ZL Compliant
- 3.3 V ±5% Supply Voltage Operation
- Fixed−Feedback for Lowest Input−To−Output Delay Variation
- SMBus Programmable Configurations to Allow Multiple Buffers in aSingle Control Network
- PLL Bypass Configurable for PLL or Fanout Operation
- Programmable PLL Bandwidth
- 2 Tri−level Addresses Selection (9 SMBUS Addresses)
- Individual OE Control Pin for Each of 12 Outputs
- 50 ps Max Output−to−Output Skew Performance
- 50 ps Max Cycle−to−Cycle Jitter (PLL mode)
- 100 ps Input to Output Delay Variation Performance
- QFN 64−pin Package, 9 mm x 9 mm
- Spread Spectrum Compatible: Tracks Input Clock Spreading for LowEMI
- 0°C to +70°C Ambient Operating Temperature
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