D Flip-Flops and JK Flip-Flops | NLSF1174

Hex D Flip-Flop with Common Clock and Reset

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概览

This device consists of six flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-tohigh transition; of the Clock input. Reset is asynchronous and active low. All inputs/outputs are standard CMOS compatible.

  • Output Drive Compatibility: 10 LSTTL Loads
  • Outpus Directly Interface to CMOS
  • Operation Voltage Range: 2 to 6 V
  • Low Input Current: 1.0 µ A
  • MSL Level 1
  • Chip Complexity: 162 FET
  • Pb-Free Package is Available

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NLSF1174MNR2G

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Lifetime

CAD Model

Pb

A

H

P

QFN-16

485G-01

1

260

REEL

3000

Y

D-Type

2

2

6

20

4

$0.2052

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可靠性数据

Die Related Summary Data

Device: NLSF1174MNR2G

Equivalent to wafer fab process: CMOS SUB

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等效器件小时

平均故障间隔时间/平均无故障时间（按小时计算）

FITS

CMOS SUB

2

920154574

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Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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