D Flip-Flops and JK Flip-Flops | MC74HC73A

Dual JK Flip Flop with Reset

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High Performance Silicon Gate CMOS. The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative edge clocked and has an active low asynchronous reset. The MC74HC73A is identical in function to the HC107, but has a different pinout.

  • Desktop

  • Output Drive Capability: 10 LSTTL Loads
  • Outputs Directly Interface to CMOS, NMOS, and TTL
  • Operating Voltage Range: 2.0 to 6.0 V
  • Low Input Current: 1.0 µA
  • High Noise Immunity Characteristic of CMOS Devices
  • In Compliance with the JEDEC Standard No. 7.0 A Requirements
  • Chip Complexity: 92 FETs or 23 Equivalent Gates
  • These are PbFree Devices

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MC74HC73ADG

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Pb

A

H

P

SOIC-14

751A-03

1

260

TUBE

55

N

JK-Type

2

2

6

21

5.2

$0.1713

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MC74HC73ADR2G

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CAD Model

Pb

A

H

P

SOIC-14

751A-03

1

260

REEL

2500

N

JK-Type

2

2

6

21

5.2

$0.1167

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MC74HC73ADTR2G

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Pb

A

H

P

TSSOP-14 WB

948G

1

260

REEL

2500

N

JK-Type

2

2

6

21

5.2

$0.1899

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可靠性数据

Die Related Summary Data

Device: MC74HC73ADG

Equivalent to wafer fab process: CMOS SUB

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等效器件小时

平均故障间隔时间/平均无故障时间（按小时计算）

FITS

CMOS SUB

2

920154574

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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