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LVX373包含八个带3态输出的锁存器,适用于总线组织的系统应用。 当锁存使能(LE)为高电平时,锁存器对于数据而言是透明的。 当LE为低电平时,满足输入时序要求的数据被锁存。 当输出使能(OE#)为低电平时,数据显示在总线上。 当OE#为高电平时,总线输出处于高阻抗状态。 输入容许电压达7V,允许5V系统到3V系统的连接。
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CAD Models
Compliance
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MSL Temp (°C)
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VCC Min (V)
VCC Max (V)
tpd Max (ns)
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74LVX373M
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74LVX373MTCX
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可靠性数据
Die Related Summary Data
Device: 74LVX373MTCX
Equivalent to wafer fab process: CMOS STD
产品技术
产品技术
等效器件小时
平均故障间隔时间/平均无故障时间(按小时计算)
FITS
CMOS STD
3
3597164517
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Re-calculate Data
Data is based on the following assumptions.
Note: The temperature and confidence level may be adjusted to your requirements.
Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)