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MC14042B 四路透明锁存在一个单片结构中使用 MOS P 沟道和 N 沟道增强模式器件构造。每个锁存均具有单独的数据输入,但所有四个锁存共享一个公共时钟。用于通过锁存频闪数据的时钟极性(高电平或低电平)可以使用极性输入进行保留。数据输入处呈现的信息在极性输入确定的时钟电平期间传输到输出 Q 和 Q。当极性输入为逻辑“0”状态时,数据在时钟低电平期间进行传输,当极性输入为逻辑“1”状态时,在时钟高电平期间进行传输。
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MC14042BDG
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MC14042BDR2G
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NLV14042BDG
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NLV14042BDR2G
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可靠性数据
Die Related Summary Data
Device: MC14042BDG
Equivalent to wafer fab process: CMOS STD
产品技术
产品技术
等效器件小时
平均故障间隔时间/平均无故障时间(按小时计算)
FITS
CMOS STD
3
3597164517
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Data is based on the following assumptions.
Note: The temperature and confidence level may be adjusted to your requirements.
Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)