Latches & Registers | MC14043B

四路 R-S 锁存

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MC14043B 和 MC14044B 四路 R-S 锁存在一个单片结构中使用 MOS P 沟道和 N 沟道增强模式器件构造。每个锁存都有一个独立的 Q 输出以及设置输入和重置输入。Q 输出通过具有共启用输入的三态缓冲器进行门极控制。这些输出在启用输入时使用逻辑“1”或高电平启用；逻辑“0”或低电平会将锁存从 Q 输出端口，在 Q 输出处产生开路。

  • Double Diode Input Protection
  • Three-State Outputs with Common Enable
  • Outputs Capable of Driving Two Low-power TTL Loads or One Low-Power Schottky TTL Load Over the Rated Temperature Range
  • Supply Voltage Range = 3.0 Vdc to 18 Vdc
  • Pb-Free Packages are Available*

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MC14043BDG

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CAD Model

Pb

A

H

P

SOIC-16

751B-05

1

260

TUBE

48

N

Latch

4

3

18

175

2.25

$0.2497

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MC14043BDR2G

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CAD Model

Pb

A

H

P

SOIC-16

751B-05

1

260

REEL

2500

N

Latch

4

3

18

175

2.25

$0.2497

More Details

NLV14043BDG

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Active

CAD Model

Pb

A

H

P

SOIC-16

751B-05

1

260

TUBE

48

N

Latch

4

3

18

175

2.25

$0.2819

More Details

NLV14043BDR2G

Contact Sales

Active

CAD Model

Pb

A

H

P

SOIC-16

751B-05

1

260

REEL

2500

N

Latch

4

3

18

175

2.25

$0.2275

More Details

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可靠性数据

Die Related Summary Data

Device: MC14043BDG

Equivalent to wafer fab process: CMOS STD

产品技术

产品技术

等效器件小时

平均故障间隔时间/平均无故障时间（按小时计算）

FITS

CMOS STD

3

3597164517

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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