Logic Gates | MM74HC138

3-8 线路解码器

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MM74HC138 解码器采用先进的硅门极 CMOS 工艺制造，非常适合内存地址解码或数据路由应用。该电路都具有高抗扰度和低功耗的特点，通常与 CMOS 电路关联，但其速度可与低功耗的肖特基 TTL 逻辑相媲美。MM74HC138 有 3 个二进制选择输入（A、B 和 C）。如果启用该器件，这些输入将确定八个正常的高电平输出中哪一个将变为低电平。提供了两个低电平有效启用和一个高电平有效启用（G1、G2A＃和 G2B＃），以简化解码器的级联。解码器的输出可驱动 10 个低功率肖特基 TTL 等效负载，并且在功能和引脚上都等效于 74LS138。通过将二极管箝位到 VCC 和接地，可防止所有输入因静电放电而受损。

  • This product is general usage and suitable for many different applications.

  • 典型传播延迟： 20 ns
  • 宽电源范围： 2V-6V
  • 低静态电流： 80 µA，最大值（74 HC系列）
  • 低输出电流： 最大值为 1 μA
  • 10 LS-TTL 负载扇出

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MM74HC138M

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751B-05

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MM74HC138MTC

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MM74HC138MTCX

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MM74HC138MX

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MM74HC138N

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可靠性数据

Die Related Summary Data

Device: MM74HC138M

Equivalent to wafer fab process: CMOS SUB

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平均故障间隔时间/平均无故障时间（按小时计算）

FITS

CMOS SUB

2

920154574

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Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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