--*************************************************************************** --* MODEL USAGE (REVISED 31MAY11 by Justin Larson, EG) --* Adapted to NCV887200 by Alain Laprade, EG (25JAN13) --* Updated 3OCT12 to adjust soft start simulation time --* (SOFTSTART1 --> slew_step was 17.5e-3, now is 5.83e-3. Soft start count in section --* 5A OPTIONAL ARCHITECTURE_1 changed from 15 to 31) * --* * --* (UVLO centered at 5.00 V with hysteresis of +/- 0.25 V) * --* The model is set up according to the standard programmed values * --* of the NCV887200. Changing values may make the model inaccurate. * --* * --* The 'generic' values in the NCV_8872 entity are programmable. * --* NOTE: Devices are programmed to pre-determined values. * --* See product datasheet for possible configurations. * --* * --* To use, create a symbol for the NCV_8872 entity and add to a schematic. * --* Then compile the entirety of this VHDL file. All models contained * --* in this file must be compiled for proper functionality. * --*************************************************************************** --`protect begin library IEEE; use IEEE.ELECTRICAL_SYSTEMS.all; use IEEE.std_logic_1164.all; entity a2d_hyst is generic ( hysteresis: VOLTAGE; threshold: VOLTAGE ); port ( terminal a: ELECTRICAL; signal d: inout std_logic ); end entity a2d_hyst; architecture default of a2d_hyst is signal ideal : std_logic := '0'; quantity v_in across a to ELECTRICAL_REF; begin process(v_in'above(threshold - hysteresis), v_in'above(threshold + hysteresis)) is begin if v_in'above(threshold + hysteresis) then d <= '1'; elsif not v_in'above(threshold - hysteresis) then d <= '0'; elsif d = '1' then if v_in'above(threshold - hysteresis) then d <= '1'; else d <= '0'; end if; elsif d = '0' then if v_in'above(threshold + hysteresis) then d <= '1'; else d <= '0'; end if; else d <= '0'; end if; end process; end architecture default; library ieee; use ieee.std_logic_1164.all; entity nor2 is generic ( delay : time := 0 ns); -- Delay time port ( in1, in2 : in std_logic; output : out std_logic); end entity nor2; architecture ideal of nor2 is begin output <= in1 nor in2 after delay; end architecture ideal; library ieee; use ieee.std_logic_1164.all; entity or2 is generic ( delay : time := 0 ns); -- Delay time port ( in1, in2 : in std_logic; output : out std_logic); end entity or2; architecture ideal of or2 is begin output <= in1 or in2 after delay; end architecture ideal; library ieee; use ieee.std_logic_1164.all; entity or3 is generic ( delay : time := 0 ns); -- Delay time port ( in1, in2, in3 : in std_logic; output : out std_logic); end entity or3; architecture ideal of or3 is begin output <= in1 or in2 or in3 after delay; end architecture ideal; library IEEE; use IEEE.electrical_systems.all; entity resistor is generic ( res : resistance); -- resistance (no initial value) port ( terminal p1, p2 : electrical); end entity resistor; ------------------------------------------------------------------------------- -- Ideal Architecture (V = I*R) ------------------------------------------------------------------------------- architecture ideal of resistor is quantity v across i through p1 to p2; begin -- Fundamental equation v == i*res; end architecture ideal; library IEEE; use IEEE.electrical_systems.all; entity capacitor is generic ( cap : capacitance; -- Capacitance [F] v_ic : real := real'low); -- Initial voltage (activated by -- IF statement below) port ( terminal p1, p2 : electrical); end entity capacitor; ------------------------------------------------------------------------------- -- Ideal Architecture (I = C * dV/dt) -- Includes initial condition ------------------------------------------------------------------------------- architecture ideal of capacitor is quantity v across i through p1 to p2; begin if domain = quiescent_domain and v_ic /= real'low use v == v_ic; else i == cap * v'dot; -- Fundamental equation end use; end architecture ideal; library IEEE; use IEEE.std_logic_1164.all; use IEEE.electrical_systems.all; entity switch_dig is generic (r_open : resistance := 1.0e6; r_closed : resistance := 0.001; trans_time : real := 1.0e-9); port (sw_state : in std_logic; terminal p1, p2 : electrical); end entity switch_dig; architecture ideal of switch_dig is signal r_sig : resistance := r_open; quantity v across i through p1 to p2; quantity r : resistance; begin -- purpose: Detect Switch state and assign resistance value to r_sig -- type : combinational -- inputs : sw_state -- outputs: r_sig DetectState: process (sw_state) begin -- process DetectState if (sw_state'event and sw_state = '0') then r_sig <= r_open; elsif (sw_state'event and sw_state = '1') then r_sig <= r_closed; end if; end process DetectState; r == r_sig'ramp(trans_time, trans_time); v == r*i; end architecture ideal; library ieee; use ieee.std_logic_1164.all; entity inv_real is generic ( delay : real := 0.0); -- Delay time port ( input : in std_logic; output : out std_logic); end entity inv_real; architecture ideal of inv_real is begin output <= not input after 1 sec*(delay); end architecture ideal; library ieee; use ieee.std_logic_1164.all; entity and2 is generic ( delay : time := 0 ns); -- Delay time port ( in1, in2 : in std_logic; output : out std_logic); end entity and2; architecture ideal of and2 is begin output <= in1 and in2 after delay; end architecture ideal; library IEEE; use IEEE.MATH_REAL.all; -- Use IEEE natures and packages use IEEE.electrical_systems.all; entity v_constant is generic ( level : voltage; -- Constant voltage value [Volts] ac_mag : voltage := 0.0; -- AC magnitude [Volts] ac_phase : real := 0.0); -- AC phase [Degrees] port ( terminal pos, neg : electrical); end entity v_constant; ------------------------------------------------------------------------------- -- Ideal Architecture (I = constant) ------------------------------------------------------------------------------- architecture ideal of v_constant is -- Declare Branch Quantities quantity v across i through pos to neg; -- Declare quantity in frequency domain for AC analysis quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0; begin if domain = quiescent_domain or domain = time_domain use v == level; else v == ac_spec; -- used for Frequency (AC) analysis end use; end architecture ideal; library IEEE; use IEEE.math_real.all; -- Use IEEE natures and packages use IEEE.electrical_systems.all; entity i_constant is generic ( level : current; -- Constant current value [Amps] ac_mag : current := 0.0; -- AC magnitude [Amps] ac_phase : real := 0.0); -- AC phase [Degrees] port ( terminal pos, neg : electrical); end entity i_constant; ------------------------------------------------------------------------------- -- Ideal Architecture (I = constant) ------------------------------------------------------------------------------- architecture ideal of i_constant is -- Declare internal quantities quantity v across i through pos to neg; -- Declare quantity in frequency domain for AC analysis quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0; begin if domain = quiescent_domain or domain = time_domain use i == level; else i == ac_spec; -- used for Frequency (AC) analysis end use; end architecture ideal; library IEEE; use IEEE.math_real.all; use IEEE.std_logic_1164.all; use IEEE.electrical_systems.all; entity a2d_bit is generic ( thres : voltage := 2.5); -- Threshold to determine logic output port ( terminal a : electrical; -- analog input signal d : out std_logic); -- digital (std_logic) output end entity a2d_bit; ------------------------------------------------------------------------------- -- Ideal architecture -- Uses 'above operator to detect threshold crossing ------------------------------------------------------------------------------- architecture ideal of a2d_bit is quantity vin across a; begin -- purpose: Detect threshold crossing and assign event on output (d) -- type : combinational -- inputs : vin'above(thres) -- outputs: pulse_signal process (vin'above(thres)) is begin -- PROCESS if vin'above(thres) then d <= '1'; else d <= '0'; end if; end process; end ideal; library IEEE; use IEEE.ELECTRICAL_SYSTEMS.all; use IEEE.MATH_REAL.all; use IEEE.std_logic_1164.all; -- ********************************************************* -- SECTION_4 DEFINITIONS AND PORTS entity logic_887200 is generic ( scp_en : std_logic := '1' -- enable short circuit protection (set to '0' to disable) ); port ( -- Note: Pins labeled as FAULT will always force gdrv_en output low signal shdwn : in std_logic; -- device shutdown signal uv_out : in std_logic; -- undervolt at VIN to chip (FAULT) signal tsout : in std_logic; -- temperature shutdown (FAULT) signal hcp_scp : in std_logic; -- short circuit protection (FAULT) signal hcp_ocp : in std_logic; -- over current protection (FAULT) signal rdy_go : in std_logic; -- device ready (forced high in 887200) (FAULT) signal vdrv_uvlo : in std_logic; -- undervolt on VDRV of chip (FAULT) signal pwmout : in std_logic; -- output of pwm comparator signal clk : in std_logic; -- device clock signal minon : in std_logic; -- minimum on time pulse signal climb : in std_logic; -- inverted current limit signal signal gdrv_en : out std_logic; -- gate drive enable output signal ramp_ctrl : out std_logic; -- control to reset slope compensation ramp (output) terminal GND: ELECTRICAL -- ground reference ); constant delay : TIME := 100 us; -- built in delay at rdy_go pin end entity logic_887200; -- ********************************************************* -- SECTION_5 ARCHITECTURE architecture default of logic_887200 is signal powdown: std_logic; -- internal logic signals signal w0: std_logic := '1'; -- w0 is set initially to allow values on all device wires signal w1: std_logic; signal w2: std_logic; signal w3: std_logic; signal w4: std_logic; signal w5: std_logic; signal w6: std_logic; signal w7: std_logic; begin -- for details of logic, see device schematic -- gdrv_en is forced low when a fault is detected -- ramp_ctrl is inverted gdrv_en signal w0 <= not rdy_go after delay; w1 <= shdwn or vdrv_uvlo or uv_out or tsout or (hcp_ocp and (not minon)) or (hcp_scp and scp_en); -- fault signal, forces device off when high powdown <= w0 or w1; w2 <= pwmout nor minon; w3 <= minon nor (climb or powdown); w4 <= w2 or w3; w5 <= w4 nor powdown; w7 <= w6 and clk; gdrv_en <= w7; ramp_ctrl <= not w7; process(clk,w5) is -- flip-flop to detect output of pwm comparator begin if w5 = '0' then -- reset flip-flop on fault, when climb and minon and powdown are low, w6 <= '0'; -- or when pwmout and minon signals are low elsif rising_edge(clk) then -- set flip-flop on clock rising edge w6 <= pwmout; else -- flip-flop keeps value if no other input is available w6 <= w6; end if; end process; end architecture default; library IEEE; use IEEE.ELECTRICAL_SYSTEMS.all; use IEEE.MATH_REAL.all; use IEEE.std_logic_1164.all; -- ********************************************************* -- SECTION_4 DEFINITIONS AND PORTS entity Oscillator_887200 is generic ( --** Global Variables** Fs: REAL := 170.0e3; -- clock operating frequency Sa: REAL := 50.0; -- slope (mV/us) of slope compensation ramp minon_time : time := 10 ns; -- minimum on time of clock signal, pulse width of minon output signal vlow : voltage := 0.01; -- analog low voltage level for digital signals vhigh : voltage := 3.3; -- analog high voltage level for digital signals Dmax : real := 0.95; -- max duty cycle percentage --** Safe Operating Area Variables** SOA_SUPPLY_MAX : VOLTAGE := 3.6; -- Max voltage for Supply Pin SOA_SUPPLY_MIN : VOLTAGE := 1.4 -- Min voltage for Digital Pin ); port ( terminal drail: ELECTRICAL; -- Digital supply rail terminal arail: ELECTRICAL; -- Analog supply rail terminal sc : ELECTRICAL; -- slope compensation output signal minon : out std_logic := '0'; -- minimum on time output signal clk : inout std_logic := '0'; -- device operating clock (runs at Fs when not syncing) signal en_clk : out std_logic := '0'; -- internal oscillator clock (slows to 70% Fs when syncing signal sync : in std_logic; -- allow syncing when high signal sc_reset : in std_logic; -- slope compensation reset (set slope comp to 0 when high) signal enable : in std_logic; -- device enable input terminal AGND: ELECTRICAL; -- Analog Ground terminal DGND: ELECTRICAL -- Digital Ground ); -- Global constants/definitions not visible to symbol user constant Ts : real := 1.0/Fs; -- oscillator period constant on_time : real := Ts * Dmax; -- clock on time constant off_time : real := Ts - on_time; -- clock off time constant slow_on : real := 0.7 * Ts * Dmax; -- internal clock on time when syncing constant slow_off : real := 0.7 * Ts - slow_on; -- internal clock off time when syncing constant Soff : real := -Sa*on_time/off_time; -- SC slope during off-time (reset) end entity Oscillator_887200; -- ********************************************************* --SECTION_5 PRIMARY ARCHITECTURE : Basic architecture Basic of Oscillator_887200 is -- *****Signal and Constant definitions ***** signal v_slope : voltage := 0.0; -- slope compensation (sets min/max level, output will slew at defined rate) signal osc : std_logic := '0'; -- *****Electrical Description of Ports***** quantity v_sc across i_sc through sc to AGND; -- slope compensation ramp output quantity v_rail_sw across i_rail_sw through drail to DGND; -- digital voltage supply rail quantity v_rail across i_rail through arail to AGND; -- analog voltage supply rail begin v_rail_sw == i_rail_sw * 100.0e3; v_rail == i_rail * 100.0e3; clk <= enable when sync = '1' else osc; en_clk <= osc; v_slope <= vlow when (clk = '0' or sc_reset = '1') else vhigh; v_sc == v_slope'slew(Sa*1.0e3,Soff*1.0e3); process is -- generate internal clock (used by enable/sync block) begin if sync = '0' then -- when not syncing osc <= '0'; -- clock is low for off_time wait for off_time; osc <= '1'; -- high for on_time wait for on_time; else -- when syncing osc <= '0'; -- clock slows to 70% of programmed frequency wait for slow_off; -- allows device to "sync down" to 70% of programmed frequency osc <= '1'; wait for slow_on; end if; end process; process(clk) is -- minimum on time pulse setup begin -- on positive clock edge, minon goes high if clk = '1' and clk'event then -- minon set low after minimum on time minon <= '1', '0' after minon_time; -- still applies when syncing else minon <= '0'; end if; end process; end architecture Basic; library IEEE; use IEEE.ELECTRICAL_SYSTEMS.all; use IEEE.MATH_REAL.all; use IEEE.std_logic_1164.all; -- ********************************************************* -- SECTION_4 DEFINITIONS AND PORTS entity Softstart is generic ( slew_start : VOLTAGE := 0.03; -- Starting level for SLEW output slew_step : VOLTAGE := 15.0e-3; -- step size of slew output for Stepped Architecture (was 15mV) step_time : time := 1 ns; -- time between steps slew_max : VOLTAGE := 1.4 -- softstart end level, when the slew ramp reaches this point, it will quickly jump to the rail voltage ); port ( terminal ARAIL: ELECTRICAL; -- Analog supply rail terminal DRAIL: ELECTRICAL; -- Digital supply rail signal CLOCK : in std_logic; -- Clock signal input terminal ISS_2utr: ELECTRICAL; -- Bias current (2uA nominal) terminal VSS_REF: ELECTRICAL; -- Reference voltage input (sets slew output max level) signal POWDOWN: in std_logic; -- Power down input signal (active high) terminal AGND: ELECTRICAL; -- Analog ground terminal DGND: ELECTRICAL; -- Digital ground terminal SLEW: ELECTRICAL; -- Slew output (increases from start point to reference level, then snaps to rail level) signal SSDONE: out std_logic -- Soft start done output signal (high when soft start has finished) ); --** Safe Operating Area Variables** constant SOA_Supply_Max : VOLTAGE := 3.0; -- Max voltage for Supply Pin constant SOA_Supply_Min : VOLTAGE := 2.8; -- Min voltage for Supply Pin constant SOA_Current_Max : CURRENT := 20.0e-6; -- Max bias current constant SOA_Current_Min : CURRENT := 1.0e-6; -- Min bias current constant logic_high : VOLTAGE := 2.7; -- Default logic high digital output level constant threshold : VOLTAGE := 1.4; -- Digital high/low threshold constant snap_time : REAL := 64.0e-6; -- Time for SLEW voltage to snap to ARAIL after reaching the reference level end entity Softstart; -- ********************************************************* -- SECTION_5 ARCHITECTURE architecture Linear of Softstart is -- *****Function Definitions Specific to Architecture***** FUNCTION time2real(tt: TIME) RETURN REAL IS begin RETURN time'pos(tt) * 1.0e-15; end function time2real; -- *****Signals and Constants Specific to Architecture***** signal slew_volt: VOLTAGE := slew_start; signal Tclk : real := 1.0/(170.0e3); signal Tave : real := 1.0/(170.0e3); signal rate : real := (1.0/6.0)*(1.2/1.28e-3); -- *****Electrical Description of Ports***** quantity v_arail across i_arail through ARAIL to AGND; -- analog supply rail quantity v_drail across i_drail through DRAIL to DGND; -- digital supply rail quantity v_iss across i_iss through ISS_2utr to AGND; -- bias current quantity v_vss across VSS_REF to AGND; -- reference voltage quantity v_slew across i_slew through SLEW to AGND; -- slew output begin v_arail == i_arail * 100.0e3; -- high impedance input v_drail == i_drail * 100.0e3; -- high impedance input v_iss == i_iss*1.0e3; -- bias current input SSDONE <= '1' when slew_volt > v_vss else '0'; -- digital 'done' output v_slew == slew_volt; -- softstart slew output -- continuously calculate clock period for softstart slew rate process(CLOCK, POWDOWN) is -- calculate average clock period variable t_edge : time := 0 ns; variable count : integer := 0; begin if rising_edge(CLOCK) and count < 3 then-- on rising edge Tclk <= time2real(NOW - t_edge); -- set current clock period t_edge := NOW; Tave <= Tclk + Tave; -- add to total time count := count + 1; elsif count = 3 then Tave <= Tave/3.0; -- average clock period else count := 4; end if; end process; process is begin wait for (step_time); if POWDOWN = '1' then -- reset output on powerdown slew_volt <= slew_start; -- break statements needed for accurate simulation break; elsif slew_volt < v_vss then -- increment output if not above reference level slew_volt <= slew_volt + 2.0*(i_iss/2.0e-6)*(1.0e-6/Tave)*(1.2/1.28e-3)*time2real(step_time); break; else -- jump to rail after reaching reference level slew_volt <= v_arail; end if; end process; assert v_arail > SOA_Supply_Min and v_drail > SOA_Supply_Min -- Check voltage supply rails min value report "Supply rail below minimum level. Device may not function as expected." severity warning; assert v_arail < SOA_Supply_Max and v_drail < SOA_Supply_Max -- Check voltage supply rails max value report "Supply voltage above maximum safe level. Simulation terminated." severity error; assert i_iss > SOA_Current_Min -- Check bias current min level report "Bias current below minimum level. Device may not function as expected." severity warning; assert i_iss < SOA_Current_Max -- Check bias current max level report "Bias current above maximum safe level. Simulation terminated." severity error; end architecture Linear; -- ********************************************************* --SECTION_5A OPTIONAL ARCHITECTURE_1 architecture Stepped of Softstart is -- *****Signals and Constants Specific to Architecture***** signal slew_volt: VOLTAGE := 0.0; signal counter : integer := 0; -- *****Electrical Description of Ports***** quantity v_arail across i_arail through ARAIL to AGND; -- analog supply rail quantity v_drail across i_drail through DRAIL to DGND; -- digital supply rail quantity v_iss across i_iss through ISS_2utr to AGND; -- bias current quantity v_vss across VSS_REF to AGND; -- reference voltage quantity v_slew across i_slew through SLEW to AGND; -- slew output begin v_slew == slew_volt; -- output voltage v_arail == i_arail * 100.0e3; -- high impedance input v_drail == i_drail * 100.0e3; -- high impedance input v_iss == i_iss*1.0e3; -- bias current input SSDONE <= '1' when v_slew'above(v_vss) else '0'; -- digital 'done' output signal -- clock cycle counter, reset when counter reaches 15 process(CLOCK) is begin if counter = 15 and rising_edge(CLOCK) then counter <= 0; elsif rising_edge(CLOCK) then counter <= counter + 1; else counter <= counter; end if; end process; -- output step voltage process(counter) is begin if POWDOWN = '1' then -- reset on device powerdown slew_volt <= slew_start; break; elsif counter = 15 and slew_volt < v_arail then -- increment output when counter reaches 31 clock cycles slew_volt <= slew_volt + slew_step; break; elsif slew_volt < v_arail then -- when reference level is reached, output jumps to rail level slew_volt <= slew_volt; else slew_volt <= v_arail; end if; end process; assert v_arail > SOA_Supply_Min and v_drail > SOA_Supply_Min -- Check voltage supply rails min value report "Supply rail below minimum level. Device may not function as expected." severity warning; assert v_arail < SOA_Supply_Max and v_drail < SOA_Supply_Max -- Check voltage supply rails max value report "Supply voltage above maximum safe level. Simulation terminated." severity error; assert i_iss > SOA_Current_Min -- Check bias current min level report "Bias current below minimum level. Device may not function as expected." severity warning; assert i_iss < SOA_Current_Max -- Check bias current max level report "Bias current above maximum safe level. Simulation terminated." severity error; end architecture Stepped; library IEEE; use IEEE.ELECTRICAL_SYSTEMS.all; use IEEE.MATH_REAL.all; use IEEE.std_logic_1164.all; -- ********************************************************* -- SECTION_4 DEFINITIONS AND PORTS entity Transconductance_Amp is generic ( --** Global Variables** in_resistance: resistance := 10.0e6; -- Device input pin resistance temp_C : real := 27.0; -- Device operating temperature threshold : real := 0.6; -- Digital logic voltage threshold C_out : real := 10.0e-12; -- Output (COMP_ESD) pin capacitance (set to 0 for ideal function) Iq : current := 50.0e-6 -- quiescent current ); port ( terminal RAIL: ELECTRICAL; -- voltage supply rail terminal FB_H: ELECTRICAL; -- test mode pin terminal V1P0: ELECTRICAL; -- 1V reference input terminal VREF: ELECTRICAL; -- positive amplifier input (typical 0.8V reference) terminal FB: ELECTRICAL; -- negative amplifier input terminal SLEW: ELECTRICAL; -- slew input for softstart NOT MODELED terminal IEA: ELECTRICAL; -- bias current input (nominal 10uA) terminal EA_TL8XB: ELECTRICAL; -- tail current scaling control terminal EA_TL4XB: ELECTRICAL; -- tail current scaling control terminal EA_TL2XB: ELECTRICAL; -- tail current scaling control terminal FB_R: ELECTRICAL; -- test mode pin NOT MODELED terminal FB_SIDE_R: ELECTRICAL; -- used by slew comparator NOT MODELED terminal REF_SIDE: ELECTRICAL; -- used by slew comparator NOT MODELED terminal FB_IBUF: ELECTRICAL; -- used by slew comparator NOT MODELED terminal COMP_IBUF: ELECTRICAL; -- test mode pin NOT MODELED terminal COMP_ESD: ELECTRICAL; -- current output terminal BG_GND: ELECTRICAL; -- bandgap ground terminal AGND: ELECTRICAL); -- analog ground --** Safe Operating Area Variables** constant SOA_Supply_Max : Real := 2.9; -- Maximum supply voltage constant SOA_Supply_Min : Real := 2.5; -- Minimum supply voltage constant SOA_Current_Min : Real := 5.0e-6; -- Minimum bias current (IEA) level constant SOA_Current_Max : Real := 15.0e-6; -- Maximum bias current (IEA) level constant SOA_Input_Min : Real := -0.1; -- Minimum feedback input voltage constant SOA_Input_Max : Real := 18.0; -- Maximum feedback input voltage constant SOA_Temp_Max : Real := 150.0; -- Maximum specified operating temperature constant SOA_Temp_Min : Real := -40.0; -- Minimum specified operating temperature end entity Transconductance_amp; -- ********************************************************* -- SECTION_5 PRIMARY ARCHITECTURE: DC -- Included Features -- Models the ideal characteristics of the transconductance amplifier -- Assumes nominal 27C temperature and full frequency range -- Output voltage clamped by diodes to 1V reference input (Vout range ~ 0.3V - 1.7V -- Output current modeled by Boltzman equation (limits output current based on bias current input) -- ********************************************************* -- SECTION_5A OPTIONAL ARCHITECTURE : TRANSIENT architecture TRANSIENT of Transconductance_amp is -- *****Signals and Constants Specific to Architecture***** terminal source : electrical; constant Routput: resistance:=1.0e6; constant Coutput: capacitance:=20.0e-12; constant Rout : resistance := 542.0; constant Rin : resistance := 10.0e6; constant gm : real := 1.2e-3; constant i_max : current := 100.0e-6; constant i_min : current := -100.0e-6; constant v_max : voltage := 2.9; constant v_min : voltage := 0.01; -- *****Electrical Description of Ports***** quantity v_rail across i_rail through RAIL to AGND; -- supply voltage quantity v_vref across VREF to AGND; -- positive amplifier reference input (typical 0.8V) quantity v_fb across i_fb through FB to AGND; -- negative amplifier input (-0.1 to 18V safely) quantity v_iea across i_iea through IEA to AGND; -- input bias current (nominal 10uA) quantity v_slew across i_slew through SLEW to AGND; -- slew input, used for softstart quantity v_comp across COMP_ESD to AGND; --quantity v_source across source to AGND; quantity v_source across i_out through AGND to source; quantity v_clampH across i_clampH through source to AGND; quantity v_clampL across i_clampL through AGND to source; quantity v_in : voltage; quantity i_ideal : current; begin v_rail == i_rail * Rin; v_fb == i_fb * Rin; v_iea == i_iea * 100.0; v_slew == i_slew * Rin; if v_slew'above(v_vref) use v_in == v_vref - v_fb; else v_in == v_slew - v_fb; end use; i_ideal == gm*v_in; if v_rail'above(SOA_SUPPLY_MIN) use if i_ideal'above(i_max) use i_out == i_max; elsif i_ideal'above(i_min) use i_out == i_ideal; else i_out == i_min; end use; else v_source == 0.0; end use; break on v_rail'above(SOA_SUPPLY_MIN); i_clampH == 1.0e-12*(exp(500.0*(v_comp-v_max)) - 1.0); i_clampL == 1.0e-12*(exp(500.0*(v_min-v_comp)) - 1.0); Rout_put: entity WORK.RESISTOR(IDEAL) generic map(RES => Routput) port map( p1 => source, p2 => AGND); Cout_put: entity WORK.CAPACITOR(IDEAL) generic map(CAP => Coutput) port map( p1 => source, p2 => AGND); Ro : entity WORK.RESISTOR(IDEAL) generic map(RES => Rout ) port map ( p1 => source, p2 => COMP_ESD); -- *****Processes or Transfer Function of Cell***** -- Safe operation area assert v_rail < SOA_Supply_Max -- Check positive supply rail (high) report "Supply voltage exceeds maximum limit. It is set to " & voltage'image(v_rail) severity error; assert temp_C > SOA_Temp_Min -- Check operating temperature (low) report "Operating temperature is below minimum specified level. Device may not function correctly." severity warning; assert temp_C < SOA_Temp_Max -- Check operating temperature (high) report "Operating temperature is above minimum specified level. Device may not function correctly." severity warning; assert i_iea < SOA_Current_Max report "Bias current at pin IEA is above the maximum specified level." severity error; assert v_fb > SOA_Input_Min and v_fb < SOA_Input_Max report "Feedback input voltage is outside specified range. Device may not function correctly." severity error; end architecture TRANSIENT; library IEEE; use IEEE.ELECTRICAL_SYSTEMS.all; use IEEE.MATH_REAL.all; use IEEE.std_logic_1164.all; -- ********************************************************* -- SECTION_4 DEFINITIONS AND PORTS entity analog_buffer is port ( terminal input: ELECTRICAL; -- input voltage terminal output: ELECTRICAL -- output voltage ); end entity analog_buffer; -- ********************************************************* -- SECTION_5 ARCHITECTURE architecture default of analog_buffer is quantity v_in across i_in through input to ELECTRICAL_REF; quantity v_out across i_out through output to ELECTRICAL_REF; begin v_in == i_in * 10.0e6; -- model input as high impedance to ground v_out == v_in; -- output is an ideal voltage source end architecture default; library IEEE; use IEEE.ELECTRICAL_SYSTEMS.all; use IEEE.MATH_REAL.all; use IEEE.std_logic_1164.all; -- ********************************************************* -- SECTION_4 DEFINITIONS AND PORTS entity pwm_comp is generic ( -- ** Global Variables ** rise_trig: VOLTAGE := 0.01; -- differential Vin needed to cause rising transition at output fall_trig: VOLTAGE := -0.01 -- differential Vin needed to cause falling transition at output ); port ( terminal VDD: ELECTRICAL; -- Supply voltage terminal VPLUS: ELECTRICAL; -- positive input pin terminal VMINUS: ELECTRICAL; -- negative input pin signal VOUT: out std_logic; -- Output voltage pin terminal VSS: ELECTRICAL -- Ground ); -- ** Global Constants ** constant SOA_Supply_Max: voltage := 15.0; -- maximum safe supply voltage constant vhigh : voltage := 3.3; -- high level output voltage constant vlow : voltage := 0.1; -- low level output voltage end entity pwm_comp; -- ********************************************************* -- SECTION_5 ARCHITECTURE architecture Basic of pwm_comp is -- *****Electrical Description of Ports***** quantity v_in across VPLUS to VMINUS; -- differntial input voltage quantity i_q through VDD to VSS; -- quiescent current through device quantity v_vdd across VDD to ELECTRICAL_REF; -- positive supply voltage quantity v_vss across VSS to ELECTRICAL_REF; -- negative supply voltage quantity v_plus across VPLUS to ELECTRICAL_REF; quantity v_minus across VMINUS to ELECTRICAL_REF; begin i_q == (v_vdd - v_vss) / 30.0e6; -- quiescent current (assumes high resistance between supply rails VOUT <= '1' when v_in'above(0.0) else '0'; -- output high when v_in is positive, low otherwise -- *****Safe Operating Conditionals***** assert v_vdd'above(vhigh) and not v_vss'above(vlow) -- Check supply rails for low voltage report "Vdd or Vss is below device operating levels." severity warning; assert not v_vdd'above(SOA_Supply_Max) and v_vss'above(-SOA_Supply_Max) -- Check supply rails for high voltage report "Vdd or Vss is above safe limits. Simulation terminated." severity warning; assert not v_plus'above(v_vdd) and v_plus'above(v_vss) and v_minus'above(v_vss) and not v_minus'above(v_vdd) -- Check that inputs are within rails report "Input voltages are outside of device supply rail levels. Device may not function correctly." severity warning; end architecture Basic; library IEEE; use IEEE.ELECTRICAL_SYSTEMS.all; use IEEE.MATH_REAL.all; use IEEE.std_logic_1164.all; -- ********************************************************* -- SECTION_4 DEFINITIONS AND PORTS entity volt_sum is port ( terminal in_1: ELECTRICAL; -- input 1 terminal in_2: ELECTRICAL; -- input 2 terminal vout: ELECTRICAL -- output voltage ); end entity volt_sum; -- ********************************************************* -- SECTION_5 ARCHITECTURE architecture default of volt_sum is quantity v1 across i1 through in_1 to ELECTRICAL_REF; quantity v2 across i2 through in_2 to ELECTRICAL_REF; quantity v_out across i_out through vout to ELECTRICAL_REF; begin v_out == v1 + v2; -- summed output v1 == i1 * 1.0e6; -- high impedance input v2 == i2 * 1.0e6; -- high impedance input end architecture default; library IEEE; use IEEE.ELECTRICAL_SYSTEMS.all; use IEEE.std_logic_1164.all; entity enable_sync is generic ( SOA_ENABLE_MAX: VOLTAGE := 40.0; -- maximum enable voltage (short to battery) SOA_SUPPLY_MAX: VOLTAGE := 3.6; -- maximum supply voltage SOA_SUPPLY_MIN: VOLTAGE := 2.5; -- minimum supply voltage ff_delay : time := 100 ns -- delay time for flip-flops and latches ); port ( terminal rail_sw : electrical; -- voltage supply rail terminal en_sync : electrical; -- enable/sync device input terminal dgnd : electrical; -- ground refence signal clk : in std_logic := '0'; -- internal device clock input (oscillator clock input, used for sync timer) signal clk_en : out std_logic := '0'; -- oscillator enable output signal (matched to digital enable input) signal sync : inout std_logic := '0'; -- sync control output signal (high when syncing) signal dev_pdwn : out std_logic := '1' -- device enable/disable control signal (high when enable is high, or when syncing) ); constant threshold : VOLTAGE := 1.4; end entity enable_sync; architecture Basic of enable_sync is quantity v_rail across i_rail through rail_sw to dgnd; -- voltage supply rail quantity v_en across en_sync to dgnd; -- enable/sync input voltage signal trans : std_logic := '0'; -- output of flip-flop storing previous value of enable input signal count_in : integer := 0; -- input to flip-flop counter for sync reset signal count_out : integer := 0; -- output of flip-flop counter for sync reset signal reset : std_logic := '1'; -- high if sync reset counter is greater than signal set : std_logic := '0'; -- high when enable transitions signal enable : std_logic := '0'; -- digital representation of enable input signal en_ff : std_logic := '0'; -- ouput of enable flip-flop begin v_rail == i_rail*100.0e3; enable <= '1' when v_en'above(threshold) else '0'; -- convert analog enable input to digital signal en_ff <= enable after (ff_delay); -- create enable flip-flop, output delayed by user-defined constant set <= en_ff xor enable; -- set SR latch of SYNC output when enable signal changes state dev_pdwn <= not (enable or sync or (not reset and not enable)); -- when not syncing or enabled, device powerdown signal is high clk_en <= enable; -- clock enable receives digital enable signal directly count_in <= count_out + 1 when count_out < 3 else 3; -- counter to determine syncing reset <= '0' when count_out < 2 else '1'; -- if enable is high or low for 3 cycles, reset the SYNC SR latch -- set/reset latch for sync output process(set,reset) is -- determine state of SYNC SR latch begin -- reset is dominant input if set = '1' and reset = '0' then sync <= '1'; elsif reset = '1' then sync <= '0'; else sync <= sync; end if; end process; process(set,clk) is -- determine state of counter begin -- if set = '1' then -- reset counter when enable changes state count_out <= 0; elsif rising_edge(clk) then -- increment counter on positive clock edge count_out <= count_in; else count_out <= count_out; end if; end process; end architecture Basic; library IEEE; use IEEE.std_logic_1164.all; use IEEE.ELECTRICAL_SYSTEMS.all; use IEEE.math_real.all; entity LDO_block is generic ( -- Under-voltage lockout level uvlo: VOLTAGE := 3.0; v_reg : VOLTAGE := 10.0; Fp : real := 1.0e3; i_max : CURRENT := 35.0e-3 ); port ( terminal vin: ELECTRICAL; terminal vout: ELECTRICAL; signal stby: in std_logic; terminal gnd: ELECTRICAL ); constant v_dout : voltage := 100.0e-3; end entity LDO_block; library IEEE; use IEEE.ELECTRICAL_SYSTEMS.all; architecture default of LDO_block is terminal src_node : electrical; terminal sw_p1 : electrical; signal sw_ctrl : std_logic; signal uvlo_detect : std_logic := '1'; quantity v_src across i_src through src_node to gnd; quantity v_lim across i_lim through sw_p1 to gnd; quantity v_in across vin to gnd; quantity v_out across vout to gnd; begin sw_ctrl <= not uvlo_detect; uvlo_detect <= '0' when v_in'above(uvlo) else '1'; if i_src'above(i_max) use i_lim == i_src - i_max; else i_lim == 1.0e-9; end use; if v_in'above(v_reg + v_dout) use v_src == v_reg; else v_src == v_in - v_dout; end use; sw : entity WORK.SWITCH_DIG(IDEAL) port map ( sw_state => sw_ctrl, p1 => sw_p1, p2 => vout ); ro : entity WORK.RESISTOR(IDEAL) generic map ( RES => 10.0e-3) port map ( p1 => src_node, p2 => sw_p1); break on v_in'above(v_reg + v_dout); end architecture default; architecture standby of LDO_block is terminal src_node : electrical; terminal sw_p1 : electrical; signal sw_ctrl : std_logic; signal uvlo_detect : std_logic := '1'; quantity v_src across i_src through src_node to gnd; quantity v_lim across i_lim through sw_p1 to gnd; quantity v_in across vin to gnd; quantity v_out across vout to gnd; begin sw_ctrl <= (not stby) or uvlo_detect; uvlo_detect <= '0' when v_in'above(uvlo) else '1'; if i_src'above(i_max) use i_lim == i_src - i_max; else i_lim == 1.0e-9; end use; if v_in'above(v_reg + v_dout) use --if sw_ctrl = '0' use -- v_src == 0.0; --else v_src == v_reg; --end use; else --if sw_ctrl = '0' use -- v_src == 0.0; --else v_src == v_in - v_dout; --end use; end use; sw : entity WORK.SWITCH_DIG(IDEAL) port map ( sw_state => sw_ctrl, p1 => sw_p1, p2 => vout ); ro : entity WORK.RESISTOR(IDEAL) generic map ( RES => 10.0e-3) port map ( p1 => src_node, p2 => sw_p1); break on v_in'above(v_reg + v_dout); break on sw_ctrl; end architecture standby; library IEEE; use IEEE.ELECTRICAL_SYSTEMS.all; use IEEE.MATH_REAL.all; use IEEE.std_logic_1164.all; -- ********************************************************* -- SECTION_4 DEFINITIONS AND PORTS entity gate_drive_887200 is generic ( current_drive: CURRENT := 200.0E-3; -- maximum output current (sinking or sourcing) current_leak: CURRENT := 10.0E-6; -- leakage current (sinking or sourcing) on_level: VOLTAGE := 3.3; -- target output high voltage off_level: VOLTAGE := 0.1 -- target output low voltage (must be above 0.0) ); port ( signal ENABLE: in std_logic; -- device enable signal terminal GDRV: ELECTRICAL; -- output port (connect to gate of FET) terminal VDRV: ELECTRICAL; -- power supply rail (must be above on_level voltage) terminal GND: ELECTRICAL -- ground reference ); end entity gate_drive_887200; -- ********************************************************* -- SECTION_5 ARCHITECTURE architecture Basic of gate_drive_887200 is quantity v_vdrv across VDRV to GND; quantity i_vdrv through VDRV to GDRV; quantity v_gdrv across i_gdrv through GDRV to GND; begin if ENABLE = '1' use -- device on state -- source current from VDRV to GDRV -- leakage from GDRV to GND i_vdrv == current_leak + (1.0 - exp(1.95*(v_gdrv - on_level))); -- source current to gdrv pin (current decays as gdrv approaches on_level) i_gdrv == current_leak; else -- device off state -- sink current from GDRV to GND -- leakage from VDRV to GDRV i_gdrv == current_leak + (1.0 - exp(-1.95*(v_gdrv - off_level))); i_vdrv == current_leak; end use; end architecture Basic; --`protect end library ieee; use ieee.electrical_systems.all; use ieee.std_logic_1164.all; use work.all; entity NCV887200 is generic ( Fs : real := 675.0e3; -- Internal oscillator clock frequency (Hz) SC_EN : std_logic := '1'; -- Enable short circuit protection (set to '0' to disable) SCR : real := 0.70; -- Short circuit threshold (percentage of 1.2V nominal bandgap reference voltage) CLR : voltage := 200.0e-3; -- Current limit threshold (mV) MON : time := 100 ns; -- Minimum on time MAXD : real := 0.92; -- Maximum duty cycle (percentage) UVR : voltage := 4.75; -- Under Voltage Threshold (V) (value represents the UVLO value without hysteresis, default hysteresis is 480mV) SA : real := 34.0; -- Slope compensation slew rate (mV/us) DRV : voltage := 8.4; -- Drive voltage (V) GDS : current := 0.575 -- Gate drive strength (A) ); port ( terminal VDRV : ELECTRICAL; -- Output of VDRV LDO terminal VIN : ELECTRICAL; -- Battery voltage input terminal VC : ELECTRICAL; -- Output of transconductance error amp terminal VFB : ELECTRICAL; -- Feedback voltage input terminal ENSYNC : ELECTRICAL; -- Enable/Sync input terminal ISNS : ELECTRICAL; -- Current sense input terminal GND : ELECTRICAL; -- Ground reference pin terminal GDRV : ELECTRICAL -- Gate Drive pin ); end entity NCV887200; architecture DEFAULT of NCV887200 is --`protect begin constant hyst_vdrv : voltage := (DRV*0.15 - DRV*0.5)/2.0; constant thres_vdrv : voltage := (DRV*0.15 + DRV*0.5)/2.0; signal RDY_GO: STD_LOGIC; terminal ARAIL: ELECTRICAL; terminal SC: ELECTRICAL; terminal IEA: ELECTRICAL; signal FB_DIG: STD_LOGIC; signal DEVICE_CLK: STD_LOGIC; signal CLK_ENABLE: STD_LOGIC; terminal DRAIL: ELECTRICAL; signal SS_DONE: STD_LOGIC; signal N1: STD_LOGIC; terminal VSUM: ELECTRICAL; signal SC_RESET: STD_LOGIC; signal N2: STD_LOGIC; terminal ISS_2U: ELECTRICAL; signal N3: STD_LOGIC; signal DEV_PDWN: STD_LOGIC; signal PWMOUT: STD_LOGIC; signal N4: STD_LOGIC; signal N5: STD_LOGIC; terminal N10: ELECTRICAL; signal OSC_CLK: STD_LOGIC; signal N6: STD_LOGIC; signal N11: STD_LOGIC; terminal BG_REF: ELECTRICAL; signal TSOUT: STD_LOGIC; signal SCP: STD_LOGIC; signal SYNC: STD_LOGIC; terminal CSA_OUT: ELECTRICAL; terminal SS_SLEW: ELECTRICAL; signal MINON: STD_LOGIC; terminal REF_1P0: ELECTRICAL; signal GDRV_EN: STD_LOGIC; signal FB_INV: STD_LOGIC; signal N01: STD_LOGIC; signal N02: STD_LOGIC; signal SS_PDWN: STD_LOGIC; signal N03: STD_LOGIC; quantity v_arail across i_arail through ARAIL to GND; quantity v_drail across i_drail through DRAIL to GND; begin if N3 = '1' use v_arail == 5.0; v_drail == 3.3; else v_arail == 0.0; v_drail == 0.0; end use; INV_OCP : entity WORK.INV_REAL(IDEAL) port map ( INPUT => N11, OUTPUT => N03 ); OCP_BLANK : entity WORK.NOR2(IDEAL) port map ( in1 => MINON, in2 => N03, output => N01); HCP_G1 : entity WORK.OR3(IDEAL) port map ( in1 => DEV_PDWN, in2 => N6, in3 => SCP, output => N02); HCP_SS : entity WORK.OR2(IDEAL) port map ( in1 => N01, in2 => N02, output => SS_PDWN); \$1I1031\ : entity WORK.INV_REAL(IDEAL) port map ( INPUT => N1, OUTPUT => N2 ); \$1I1035\ : entity WORK.INV_REAL(IDEAL) port map ( INPUT => N5, OUTPUT => N6 ); \$1I1037\ : entity WORK.INV_REAL(IDEAL) port map ( INPUT => N3, OUTPUT => N4 ); A2D_BIT9 : entity WORK.A2D_BIT(IDEAL) generic map ( THRES => 6.0 ) port map ( A => ELECTRICAL_REF, D => TSOUT ); \$1I1040\ : entity WORK.INV_REAL(IDEAL) port map ( INPUT => DEV_PDWN, OUTPUT => RDY_GO ); -- V10 : entity WORK.V_CONSTANT(IDEAL) -- generic map ( LEVEL => 5.0 ) -- port map ( POS => ARAIL, -- NEG => ELECTRICAL_REF ); -- V11 : entity WORK.V_CONSTANT(IDEAL) -- generic map ( LEVEL => 3.3 ) -- port map ( POS => DRAIL, -- NEG => ELECTRICAL_REF ); V14 : entity WORK.V_CONSTANT(IDEAL) generic map ( LEVEL => 1.2 ) port map ( POS => CSA_OUT, NEG => N10 ); \$1I1056\ : entity WORK.INV_REAL(IDEAL) port map ( INPUT => FB_DIG, OUTPUT => FB_INV ); I2 : entity WORK.I_CONSTANT(IDEAL) generic map ( LEVEL => 10.0E-6 ) port map ( POS => ARAIL, NEG => IEA ); I1 : entity WORK.I_CONSTANT(IDEAL) generic map ( LEVEL => 2.0E-6 ) port map ( POS => ARAIL, NEG => ISS_2U ); V2 : entity WORK.V_CONSTANT(IDEAL) generic map ( LEVEL => 1.2 ) port map ( POS => BG_REF, NEG => ELECTRICAL_REF ); A2D_BIT10 : entity WORK.A2D_BIT(IDEAL) generic map ( THRES => 600.0E-3 ) port map ( A => N10, D => N11 ); V1 : entity WORK.V_CONSTANT(IDEAL) generic map ( LEVEL => 1.0 ) port map ( POS => REF_1P0, NEG => ELECTRICAL_REF ); A2D_BIT8 : entity WORK.A2D_BIT(IDEAL) generic map ( THRES => SCR*1.2 ) port map ( A => VFB, D => FB_DIG ); -- change to hysteretic VDRV_UVLO : entity WORK.A2D_HYST(DEFAULT) generic map ( hysteresis => hyst_vdrv, threshold => thres_vdrv ) port map ( A => VDRV, D => N5 ); -- A2D_BIT2 : entity WORK.A2D_BIT(IDEAL) -- generic map ( THRES => 0. ) -- port map ( A => VDRV, -- D => N5 ); LOGIC1 : entity WORK.LOGIC_887200(DEFAULT) generic map ( scp_en => SC_EN ) port map ( SHDWN => DEV_PDWN, UV_OUT => N4, TSOUT => TSOUT, HCP_SCP => SCP, HCP_OCP => N11, RDY_GO => RDY_GO, VDRV_UVLO => N6, PWMOUT => PWMOUT, CLK => DEVICE_CLK, MINON => MINON, CLIMB => N2, GDRV_EN => GDRV_EN, RAMP_CTRL => SC_RESET, GND => ELECTRICAL_REF ); A2D_BIT7 : entity WORK.A2D_BIT(IDEAL) generic map ( THRES => CLR ) port map ( A => N10, D => N1 ); AND2_1 : entity WORK.AND2(IDEAL) port map ( IN1 => SS_DONE, IN2 => FB_INV, OUTPUT => SCP ); OSCILLATOR2 : entity WORK.OSCILLATOR_887200(BASIC) generic map ( Fs => Fs, Sa => SA, minon_time => MON, Dmax => MAXD ) port map ( ARAIL => ARAIL, DRAIL => DRAIL, SC => SC, MINON => MINON, CLK => DEVICE_CLK, EN_CLK => OSC_CLK, SYNC => SYNC, SC_RESET => SC_RESET, ENABLE => CLK_ENABLE, AGND => ELECTRICAL_REF, DGND => ELECTRICAL_REF ); SOFTSTART1 : entity WORK.SOFTSTART(STEPPED) generic map ( SLEW_START => 0.01, SLEW_STEP => 17.5E-3 ) port map ( ARAIL => ARAIL, DRAIL => DRAIL, CLOCK => DEVICE_CLK, ISS_2UTR => ISS_2U, VSS_REF => BG_REF, POWDOWN => SS_PDWN, AGND => ELECTRICAL_REF, DGND => ELECTRICAL_REF, SLEW => SS_SLEW, SSDONE => SS_DONE ); ERROR_AMP1 : entity WORK.TRANSCONDUCTANCE_AMP(TRANSIENT) port map ( RAIL => ARAIL, FB_H => ELECTRICAL_REF, V1P0 => REF_1P0, VREF => BG_REF, FB => VFB, SLEW => SS_SLEW, IEA => IEA, EA_TL8XB => ELECTRICAL_REF, EA_TL4XB => ELECTRICAL_REF, EA_TL2XB => ELECTRICAL_REF, FB_R => ELECTRICAL_REF, FB_SIDE_R => ELECTRICAL_REF, REF_SIDE => ELECTRICAL_REF, FB_IBUF => ELECTRICAL_REF, COMP_IBUF => ELECTRICAL_REF, COMP_ESD => VC, BG_GND => ELECTRICAL_REF, AGND => ELECTRICAL_REF ); BUF2 : entity WORK.ANALOG_BUFFER(DEFAULT) port map ( INPUT => ISNS, OUTPUT => N10 ); PWM_COMP2 : entity WORK.PWM_COMP(BASIC) port map ( VDD => ARAIL, VPLUS => VC, VMINUS => VSUM, VOUT => PWMOUT, VSS => ELECTRICAL_REF ); SUM1 : entity WORK.VOLT_SUM(DEFAULT) port map ( IN_1 => SC, IN_2 => CSA_OUT, VOUT => VSUM ); ENABLE_SYNC1 : entity WORK.ENABLE_SYNC(BASIC) port map ( RAIL_SW => DRAIL, EN_SYNC => ENSYNC, DGND => ELECTRICAL_REF, CLK => OSC_CLK, CLK_EN => CLK_ENABLE, SYNC => SYNC, DEV_PDWN => DEV_PDWN ); GDRV1 : entity WORK.GATE_DRIVE_887200(BASIC) generic map ( CURRENT_DRIVE => GDS, ON_LEVEL => DRV ) port map ( ENABLE => GDRV_EN, GDRV => GDRV, VDRV => VDRV, GND => ELECTRICAL_REF ); LDO4 : entity WORK.LDO_BLOCK(STANDBY) generic map ( v_reg => DRV, uvlo => 0.5*DRV ) port map ( VIN => VIN, VOUT => VDRV, STBY => DEV_PDWN, GND => ELECTRICAL_REF ); -- change to hysteretic VIN_UVLO : entity WORK.A2D_HYST(DEFAULT) generic map ( hysteresis => 0.25, threshold => 5.00 ) port map ( A => VIN, D => N3 ); -- A2D_BIT5 : entity WORK.A2D_BIT(IDEAL) -- generic map ( THRES => UVR ) -- port map ( A => VIN, -- D => N3 ); --`protect end end architecture DEFAULT;