Design Name C:/Users/ffyrjf/Documents/PCB_Designs/ONSEC-18-030_Strata_LED_Platform/pp/YAQUINA_BAY_LED_BOARD_SEPARATE_SECTIONS.brd
Date Mon Feb 04 14:27:54 2019
DRC Error Count Summary
DRC Error Type DRC Error Count
Package to Package 1
Total DRC Errors 1

Detailed DRC Errors
Constraint Name DRC Marker Location Required Value Actual Value Constraint Source Constraint Source Type Element 1 Element 2 Comment
Package to Package Spacing (610.6 163.5) 0 MIL 0.6 MIL NONE DESIGN Filled Rectangle "C34 Package Geometry/Place_Bound_Top" Shape "J16 Package Geometry/Place_Bound_Top"