Small Signal MOSFETs | FDC6321C

双 N 和 P 沟道，数字 FET，25V

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概览

此类双 N 和 P 沟道逻辑电平增强型场效应晶体管是使用高单元密度的 DMOS 专属技术生产的。这种极高密度工艺特别适用于最大程度降低导通电阻。此器件适合在低压应用中替代负载开关应用中的数字晶体管。因为无需偏置电阻，所以此类双数字 FET 可以替代若干具有各种偏置电阻的数字晶体管。

  • This product is general usage and suitable for many different applications.

  • N-Ch 25 V, 0.68 A, RDS(ON) = 0.45 Ω @ VGS= 4.5 V
  • P-Ch -25 V, -0.46 A, RDS(ON) = 1.1 Ω @ VGS= -4.5 V.
  • 极低的栅极驱动要求允许3V电路的直接运行。 VGS(th)< 1.0V。
  • 栅-源齐纳二极管增强耐静电放电(ESD)能力。 >6kV人体模型
  • 替代多个双通道NPN & PNP数字晶体管。

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Package Name

Type

Gate Level

Wide SOA Mosfets

Configuration

OPN in older Technology

V(BR)DSS Min (V)

RDS(on) Max @ VGS = 10 V (mΩ)

VGS Max (V)

Vgs(th) Max (V)

Id Max (A)

PD Max (W)

RDS(on) Max @ VGS = 2.5 V (mΩ)

RDS(on) Max @ VGS = 4.5 V (mΩ)

Qg Typ @ VGS = 4.5 V (nC)

Qg Typ @ VGS = 10 V (nC)

Ciss Typ (pF)

Qgd Typ @ VGS = 4.5 V (nC)

Qrr Typ (nC)

Coss Typ (pF)

Crss Typ (pF)

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FDC6321C

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CAD Model

Pb

A

H

P

TSOT-23-6

419BL

1

260

REEL

3000

Y

Complementary

PowerTrench® T1

SC-6

Small Signal

Logic

0

Dual

0

±25

-

-8

1.5

N: 0.68 , P: -0.46

0.9

N: 600, P:1500

N: 450, P:1100

-

1.1

63

-

-

-

-

$0.184

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可靠性数据

Die Related Summary Data

Device: FDC6321C

Equivalent to wafer fab process: TP

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等效器件小时

平均故障间隔时间/平均无故障时间（按小时计算）

FITS

TP

8

738717284

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Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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