Small Signal MOSFETs | FDG6301N

双 N 沟道数字 FET 25V，0.22A，4Ω

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概览

此类双 N 沟道逻辑电平增强型场效应晶体管是使用专属的高单元密度 DMOS 技术生产的。这种极高密度工艺特别适用于最大程度降低导通电阻。此器件专用于在低压应用中替代双极数字晶体管和小信号 MOSFET。

  • This product is general usage and suitable for many different applications.

  • 25 V、0.22 A（连续值）、0.65 A（峰值）。
  • RDS(ON) = 4 Ω @ VGS = 4.5 V，
  • RDS(ON) = 5 Ω @ VGS = 2.7 V。
  • 电平栅极驱动要求极低，从而可在3V电路中直接运行(VGS(th)< 1.5 V)。
  • 栅-源齐纳二极管增强耐静电放电(ESD)能力（>6kV人体模型）。
  • 紧凑的工业标准SC70-6表面贴装封装。

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状态

CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Channel Polarity

Silicon Family

Package Name

Type

Gate Level

Wide SOA Mosfets

Configuration

OPN in older Technology

V(BR)DSS Min (V)

RDS(on) Max @ VGS = 10 V (mΩ)

VGS Max (V)

Vgs(th) Max (V)

Id Max (A)

PD Max (W)

RDS(on) Max @ VGS = 2.5 V (mΩ)

RDS(on) Max @ VGS = 4.5 V (mΩ)

Qg Typ @ VGS = 4.5 V (nC)

Qg Typ @ VGS = 10 V (nC)

Ciss Typ (pF)

Qgd Typ @ VGS = 4.5 V (nC)

Qrr Typ (nC)

Coss Typ (pF)

Crss Typ (pF)

Reference Price

FDG6301N

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Lifetime

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CAD Model

Pb

A

H

P

SC-88-6 / SC-70-6 / SOT-363-6

419B-02

1

260

REEL

3000

N

N-Channel

PowerTrench® T1

SC-6

Small Signal

Logic

0

Dual

0

25

-

8

1.5

0.22

0.3

Q1=Q2=5000

Q1=Q2=4000

1.64

0.29

9.5

-

-

-

-

$0.1259

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可靠性数据

Die Related Summary Data

Device: FDG6301N

Equivalent to wafer fab process: TP

产品技术

产品技术

等效器件小时

平均故障间隔时间/平均无故障时间（按小时计算）

FITS

TP

8

738717284

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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