Drivers & Fanout Buffers | NB4N121K
概览
The NB4N121K is a Clock differential input fanout distribution 1 to 21 HCSL level differential outputs, optimized for ultra low propagation delay variation. The NB4N121K is designed with HCSL clock distribution for FBDIMM applications in mind. Inputs can accept differential LVPECL, CML, or LVDS levels. Single-ended LVPECL, CML, LVCMOS or LVTTL levels are accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12, and 13). Clock input pins incorporate an internal 50 ohm on die termination resistors.
- FBDIMM Clock Distribution
- PCIe I, II, III
- Networking
- Clock Distribution
- High End Computing
- FBDIMM Memory Support
- Servers
- Routers
- Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and400 MHz
- 340 ps Typical Rise and Fall Times
- 800 ps Typical Propagation Delay tPD 100 ps Maximum Propagation
- Delta tPD 100 ps Maximum Propagation Delay Variation Per Each Differential Pair
- <1 ps RMS Additive Clock jitter
- Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
- Differential HCSL Output Level (700 mV Peak-to-Peak)
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