The portfolio of Skew Management devices from ON Semiconductor includes high-performance Programmable Delay Chips (PDC) designed primarily for clock deskewing and timing adjustment. They provide a programmable variable delay of a differential input signal. They provide ECL, LVDS, CML, LVPECL, LVCMOS or LVTTL logic level inputs and ECL, CML, or LVPECL outputs. The ideal performance characteristics and features of the portfolio include 10 or 11 ps delay increments, Open Input Default State, Safety Clamp-on Inputs, and A Logic High on the ENbar Pin Will Force Q to Logic Low. Applications include adjustable signal path delays in Automated Test Equipment (ATE) and as a general-purpose data and clock interface.
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