D Flip-Flops and JK Flip-Flops | MC74AC273

八路 D 型 触发器

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MC74AC273/74ACT273 具有八个带 独立 D 输入和 Q 输出的边沿触发 D 型触发器。公用缓冲时钟 (CP) 和主 重置（MR）输入可同时加载和重置（清除）所有触发器。该寄存器为全边沿触发。每个 D 输入的状态，在从低电平至高电平时钟转换 之前的一个设置时间内被传送到相应 触发器的 Q 输出。所有输出将被 MR 输入上的低电平 电压电平强制为低电平，而不受时钟或数据输入的影响。该器件对于仅需要真实 输出且所有存储 元件都公用的时钟和主重置的应用非常有用。

  • Ideal Buffer for MOS Microprocessor or Memory
  • Eight Edge-Triggered D Flip-Flops
  • Buffered Common Clock
  • Buffered, Asynchronous Master Reset
  • See MC74AC377 for Clock Enable Version
  • See MC74AC373 for Transparent Latch Version
  • See MC74AC374 for 3-State Version
  • Outputs Source/Sink 24 mA
  • ACT273 Has TTL Compatible Inputs
  • Pb-Free Packages are Available

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MC74AC273DTR2G

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CAD Model

Pb

A

H

P

TSSOP-20

9.48

1

260

REEL

2500

N

D-Type

8

2

6

10

24

$0.3475

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MC74AC273DWG

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CAD Model

Pb

A

H

P

SOIC-20W

751D-05

3

260

TUBE

38

N

D-Type

8

2

6

10

24

$0.4731

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MC74AC273DWR2G

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CAD Model

Pb

A

H

P

SOIC-20W

751D-05

3

260

REEL

1000

N

D-Type

8

2

6

10

24

$0.4545

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可靠性数据

Die Related Summary Data

Device: MC74AC273DTR2G

Equivalent to wafer fab process: CMOS SUB

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等效器件小时

平均故障间隔时间/平均无故障时间（按小时计算）

FITS

CMOS SUB

2

920154574

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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